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iommu/vt-d: Remove incorrect PSI capability check

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commit f81b846dcd9a1e6d120f73970a9a98b7fcaaffba upstream.

The PSI (Page Selective Invalidation) bit in the capability register
is only valid for second-level translation. Intel IOMMU supporting
scalable mode must support page/address selective IOTLB invalidation
for first-level translation. Remove the PSI capability check in SVA
cache invalidation code.

Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Lu Baolu 2019-11-20 14:10:16 +08:00 committed by Greg Kroah-Hartman
parent 632a300260
commit 6f2c72738d
1 changed files with 1 additions and 5 deletions
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6
drivers/iommu/intel-svm.c
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@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
{
struct qi_desc desc;
/*
* Do PASID granu IOTLB invalidation if page selective capability is
* not available.
*/
if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) {
if (pages == -1) {
desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
QI_EIOTLB_DID(sdev->did) |
QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |