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net: phy: qcom: create and move functions to shared library

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Create and move functions to shared library in preparation for qca83xx
PHY Family to be detached from at803x driver.

Only the shared defines are moved to the shared qcom.h header.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Christian Marangi 2024-01-29 15:15:20 +01:00 committed by Jakub Kicinski
parent 9e56ff53b4
commit 6fb760972c
5 changed files with 94 additions and 67 deletions
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4
drivers/net/phy/qcom/Kconfig
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@ -1,6 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
config QCOM_NET_PHYLIB
tristate
config AT803X_PHY
tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
select QCOM_NET_PHYLIB
depends on REGULATOR
help
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal

1
drivers/net/phy/qcom/Makefile
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@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o
obj-$(CONFIG_AT803X_PHY) += at803x.o

69
drivers/net/phy/qcom/at803x.c
View File

@ -22,6 +22,8 @@
#include <linux/sfp.h>
#include <dt-bindings/net/qca-ar803x.h>
#include "qcom.h"
#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
#define AT803X_SFC_ASSERT_CRS BIT(11)
#define AT803X_SFC_FORCE_LINK BIT(10)
@ -84,9 +86,6 @@
#define AT803X_REG_CHIP_CONFIG 0x1f
#define AT803X_BT_BX_REG_SEL 0x8000
#define AT803X_DEBUG_ADDR 0x1D
#define AT803X_DEBUG_DATA 0x1E
#define AT803X_MODE_CFG_MASK 0x0F
#define AT803X_MODE_CFG_BASET_RGMII 0x00
#define AT803X_MODE_CFG_BASET_SGMII 0x01
@ -103,19 +102,6 @@
#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
#define AT803X_DEBUG_REG_3C 0x3C
#define AT803X_DEBUG_REG_GREEN 0x3D
@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
enum stat_access_type {
PHY,
MMD
};
struct at803x_hw_stat {
const char *string;
u8 reg;
u32 mask;
enum stat_access_type access_type;
};
static struct at803x_hw_stat qca83xx_hw_stats[] = {
{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
@ -439,45 +413,6 @@ struct at803x_context {
u16 led_control;
};
static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
{
int ret;
ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
if (ret < 0)
return ret;
return phy_write(phydev, AT803X_DEBUG_DATA, data);
}
static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
{
int ret;
ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
if (ret < 0)
return ret;
return phy_read(phydev, AT803X_DEBUG_DATA);
}
static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
u16 clear, u16 set)
{
u16 val;
int ret;
ret = at803x_debug_reg_read(phydev, reg);
if (ret < 0)
return ret;
val = ret & 0xffff;
val &= ~clear;
val |= set;
return phy_write(phydev, AT803X_DEBUG_DATA, val);
}
static int at803x_write_page(struct phy_device *phydev, int page)
{
int mask;

53
drivers/net/phy/qcom/qcom-phy-lib.c Normal file
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@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/phy.h>
#include <linux/module.h>
#include "qcom.h"
MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_LICENSE("GPL");
int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
{
int ret;
ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
if (ret < 0)
return ret;
return phy_read(phydev, AT803X_DEBUG_DATA);
}
EXPORT_SYMBOL_GPL(at803x_debug_reg_read);
int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
u16 clear, u16 set)
{
u16 val;
int ret;
ret = at803x_debug_reg_read(phydev, reg);
if (ret < 0)
return ret;
val = ret & 0xffff;
val &= ~clear;
val |= set;
return phy_write(phydev, AT803X_DEBUG_DATA, val);
}
EXPORT_SYMBOL_GPL(at803x_debug_reg_mask);
int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
{
int ret;
ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
if (ret < 0)
return ret;
return phy_write(phydev, AT803X_DEBUG_DATA, data);
}
EXPORT_SYMBOL_GPL(at803x_debug_reg_write);

34
drivers/net/phy/qcom/qcom.h Normal file
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@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define AT803X_DEBUG_ADDR 0x1D
#define AT803X_DEBUG_DATA 0x1E
#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
enum stat_access_type {
PHY,
MMD
};
struct at803x_hw_stat {
const char *string;
u8 reg;
u32 mask;
enum stat_access_type access_type;
};
int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
u16 clear, u16 set);
int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);