mmc: Merge branch fixes into next
Merge the mmc fixes for v6.7-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.8. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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6fc0ca1791
@ -874,9 +874,10 @@ static const struct block_device_operations mmc_bdops = {
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static int mmc_blk_part_switch_pre(struct mmc_card *card,
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unsigned int part_type)
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{
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const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;
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int ret = 0;
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if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {
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if ((part_type & mask) == mask) {
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if (card->ext_csd.cmdq_en) {
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ret = mmc_cmdq_disable(card);
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if (ret)
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@ -891,9 +892,10 @@ static int mmc_blk_part_switch_pre(struct mmc_card *card,
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static int mmc_blk_part_switch_post(struct mmc_card *card,
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unsigned int part_type)
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{
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const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;
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int ret = 0;
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if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {
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if ((part_type & mask) == mask) {
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mmc_retune_unpause(card->host);
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if (card->reenable_cmdq && !card->ext_csd.cmdq_en)
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ret = mmc_cmdq_enable(card);
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@ -3185,4 +3187,3 @@ module_exit(mmc_blk_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");
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@ -269,7 +269,7 @@ static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
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static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct meson_mx_sdhc_host *host = mmc_priv(mmc);
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u32 rx_clk_phase;
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u32 val, rx_clk_phase;
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int ret;
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meson_mx_sdhc_disable_clks(mmc);
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@ -290,27 +290,11 @@ static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
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mmc->actual_clock = clk_get_rate(host->sd_clk);
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/*
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* according to Amlogic the following latching points are
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* selected with empirical values, there is no (known) formula
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* to calculate these.
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* Phase 90 should work in most cases. For data transmission,
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* meson_mx_sdhc_execute_tuning() will find a accurate value
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*/
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if (mmc->actual_clock > 100000000) {
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rx_clk_phase = 1;
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} else if (mmc->actual_clock > 45000000) {
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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rx_clk_phase = 15;
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else
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rx_clk_phase = 11;
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} else if (mmc->actual_clock >= 25000000) {
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rx_clk_phase = 15;
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} else if (mmc->actual_clock > 5000000) {
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rx_clk_phase = 23;
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} else if (mmc->actual_clock > 1000000) {
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rx_clk_phase = 55;
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} else {
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rx_clk_phase = 1061;
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}
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regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
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rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4;
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regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
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MESON_SDHC_CLK2_RX_CLK_PHASE,
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FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
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