net: phy: dp83867: enable robust auto-mdix
[ Upstream commit 5a7f08c2abb0efc9d17aff2fc75d6d3b85e622e4 ] The link detection timeouts can be observed (or link might not be detected at all) when dp83867 PHY is configured in manual mode (speed/duplex). CFG3[9] Robust Auto-MDIX option allows to significantly improve link detection in case dp83867 is configured in manual mode and reduce link detection time. As per DM: "If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force 100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock." Hence, enable this option by default as there are no known reasons not to do so. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -84,6 +84,10 @@
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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/* CFG3 bits */
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#define DP83867_CFG3_INT_OE BIT(7)
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#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
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/* CFG4 bits */
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#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
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@ -320,12 +324,13 @@ static int dp83867_config_init(struct phy_device *phydev)
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return ret;
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}
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val = phy_read(phydev, DP83867_CFG3);
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/* Enable Interrupt output INT_OE in CFG3 register */
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if (phy_interrupt_is_valid(phydev)) {
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val = phy_read(phydev, DP83867_CFG3);
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val |= BIT(7);
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phy_write(phydev, DP83867_CFG3, val);
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}
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if (phy_interrupt_is_valid(phydev))
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val |= DP83867_CFG3_INT_OE;
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val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
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phy_write(phydev, DP83867_CFG3, val);
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if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
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dp83867_config_port_mirroring(phydev);
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