Miscellaneous ia64 fixes from Christoph
-----BEGIN PGP SIGNATURE----- iIoEABYIADIWIQQW3WBGcnu5yJnSXn0kTJLX0iGMLAUCW84v0RQcdG9ueS5sdWNr QGludGVsLmNvbQAKCRAkTJLX0iGMLGJGAP9fUhp7O4ef6PHxGtvmKHRqkTX6a4b5 /oASkd4qIetgzAEA7hwUopUllbq13IRqc+1Z93wymj4vGjT+jV+2unI0ZAc= =3Yoq -----END PGP SIGNATURE----- Merge tag 'please-pull-next' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux Pull ia64 updates from Tony Luck: "Miscellaneous ia64 fixes from Christoph" * tag 'please-pull-next' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux: intel-iommu: mark intel_dma_ops static ia64: remove machvec_dma_sync_{single,sg} ia64/sn2: remove no-ops dma sync methods ia64: remove the unused iommu_dma_init function ia64: remove the unused pci_iommu_shutdown function ia64: remove the unused bad_dma_address symbol ia64: remove iommu_dma_supported ia64: remove the dead iommu_sac_force variable ia64: remove the kern_mem_attribute export
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70408a9987
@ -2207,10 +2207,6 @@ const struct dma_map_ops sba_dma_ops = {
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.unmap_page = sba_unmap_page,
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.map_sg = sba_map_sg_attrs,
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.unmap_sg = sba_unmap_sg_attrs,
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.sync_single_for_cpu = machvec_dma_sync_single,
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.sync_sg_for_cpu = machvec_dma_sync_sg,
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.sync_single_for_device = machvec_dma_sync_single,
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.sync_sg_for_device = machvec_dma_sync_sg,
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.dma_supported = sba_dma_supported,
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.mapping_error = sba_dma_mapping_error,
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};
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@ -14,11 +14,6 @@ extern const struct dma_map_ops *dma_ops;
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extern struct ia64_machine_vector ia64_mv;
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extern void set_iommu_machvec(void);
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extern void machvec_dma_sync_single(struct device *, dma_addr_t, size_t,
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enum dma_data_direction);
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extern void machvec_dma_sync_sg(struct device *, struct scatterlist *, int,
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enum dma_data_direction);
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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return platform_dma_get_ops(NULL);
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@ -5,7 +5,6 @@
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/* 10 seconds */
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#define DMAR_OPERATION_TIMEOUT (((cycles_t) local_cpu_data->itc_freq)*10)
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extern void pci_iommu_shutdown(void);
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extern void no_iommu_init(void);
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#ifdef CONFIG_INTEL_IOMMU
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extern int force_iommu, no_iommu;
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@ -16,7 +15,6 @@ extern int iommu_detected;
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#define no_iommu (1)
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#define iommu_detected (0)
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#endif
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extern void iommu_dma_init(void);
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extern void machvec_init(const char *name);
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#endif
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@ -842,7 +842,6 @@ kern_mem_attribute (unsigned long phys_addr, unsigned long size)
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} while (md);
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return 0; /* never reached */
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}
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EXPORT_SYMBOL(kern_mem_attribute);
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int
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valid_phys_addr_range (phys_addr_t phys_addr, unsigned long size)
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@ -73,19 +73,3 @@ machvec_timer_interrupt (int irq, void *dev_id)
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{
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}
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EXPORT_SYMBOL(machvec_timer_interrupt);
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void
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machvec_dma_sync_single(struct device *hwdev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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mb();
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}
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EXPORT_SYMBOL(machvec_dma_sync_single);
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void
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machvec_dma_sync_sg(struct device *hwdev, struct scatterlist *sg, int n,
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enum dma_data_direction dir)
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{
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mb();
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}
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EXPORT_SYMBOL(machvec_dma_sync_sg);
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@ -15,11 +15,6 @@
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#include <linux/kernel.h>
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#include <asm/page.h>
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dma_addr_t bad_dma_address __read_mostly;
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EXPORT_SYMBOL(bad_dma_address);
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static int iommu_sac_force __read_mostly;
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int no_iommu __read_mostly;
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#ifdef CONFIG_IOMMU_DEBUG
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int force_iommu __read_mostly = 1;
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@ -29,8 +24,6 @@ int force_iommu __read_mostly;
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int iommu_pass_through;
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extern struct dma_map_ops intel_dma_ops;
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static int __init pci_iommu_init(void)
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{
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if (iommu_detected)
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@ -42,56 +35,8 @@ static int __init pci_iommu_init(void)
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/* Must execute after PCI subsystem */
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fs_initcall(pci_iommu_init);
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void pci_iommu_shutdown(void)
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{
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return;
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}
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void __init
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iommu_dma_init(void)
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{
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return;
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}
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int iommu_dma_supported(struct device *dev, u64 mask)
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{
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/* Copied from i386. Doesn't make much sense, because it will
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only work for pci_alloc_coherent.
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The caller just has to use GFP_DMA in this case. */
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if (mask < DMA_BIT_MASK(24))
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return 0;
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/* Tell the device to use SAC when IOMMU force is on. This
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allows the driver to use cheaper accesses in some cases.
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Problem with this is that if we overflow the IOMMU area and
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return DAC as fallback address the device may not handle it
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correctly.
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As a special case some controllers have a 39bit address
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mode that is as efficient as 32bit (aic79xx). Don't force
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SAC for these. Assume all masks <= 40 bits are of this
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type. Normally this doesn't make any difference, but gives
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more gentle handling of IOMMU overflow. */
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if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
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dev_info(dev, "Force SAC with mask %llx\n", mask);
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return 0;
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}
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return 1;
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}
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EXPORT_SYMBOL(iommu_dma_supported);
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void __init pci_iommu_alloc(void)
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{
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dma_ops = &intel_dma_ops;
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intel_dma_ops.sync_single_for_cpu = machvec_dma_sync_single;
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intel_dma_ops.sync_sg_for_cpu = machvec_dma_sync_sg;
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intel_dma_ops.sync_single_for_device = machvec_dma_sync_single;
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intel_dma_ops.sync_sg_for_device = machvec_dma_sync_sg;
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intel_dma_ops.dma_supported = iommu_dma_supported;
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/*
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* The order of these functions is important for
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* fall-back/fail-over reasons
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@ -314,31 +314,6 @@ static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
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return nhwentries;
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}
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static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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BUG_ON(!dev_is_pci(dev));
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}
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static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return 0;
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@ -466,10 +441,6 @@ static struct dma_map_ops sn_dma_ops = {
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.unmap_page = sn_dma_unmap_page,
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.map_sg = sn_dma_map_sg,
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.unmap_sg = sn_dma_unmap_sg,
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.sync_single_for_cpu = sn_dma_sync_single_for_cpu,
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.sync_sg_for_cpu = sn_dma_sync_sg_for_cpu,
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.sync_single_for_device = sn_dma_sync_single_for_device,
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.sync_sg_for_device = sn_dma_sync_sg_for_device,
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.mapping_error = sn_dma_mapping_error,
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.dma_supported = sn_dma_supported,
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.get_required_mask = sn_dma_get_required_mask,
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@ -3895,7 +3895,7 @@ static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
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return !dma_addr;
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}
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const struct dma_map_ops intel_dma_ops = {
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static const struct dma_map_ops intel_dma_ops = {
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.alloc = intel_alloc_coherent,
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.free = intel_free_coherent,
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.map_sg = intel_map_sg,
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@ -3903,9 +3903,7 @@ const struct dma_map_ops intel_dma_ops = {
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.map_page = intel_map_page,
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.unmap_page = intel_unmap_page,
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.mapping_error = intel_mapping_error,
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#ifdef CONFIG_X86
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.dma_supported = dma_direct_supported,
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#endif
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};
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static inline int iommu_domain_cache_init(void)
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