ice: Implement driver functionality to dump serdes equalizer values
To debug link issues in the field, serdes Tx/Rx equalizer values
help to determine the health of serdes lane.
Extend 'ethtool -d' option to dump serdes Tx/Rx equalizer.
The following list of equalizer param is supported
a. rx_equalization_pre2
b. rx_equalization_pre1
c. rx_equalization_post1
d. rx_equalization_bflf
e. rx_equalization_bfhf
f. rx_equalization_drate
g. tx_equalization_pre1
h. tx_equalization_pre3
i. tx_equalization_atten
j. tx_equalization_post1
k. tx_equalization_pre2
Reviewed-by: Simon Horman <horms@kernel.org>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Anil Samal <anil.samal@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Link: https://patch.msgid.link/20240709202951.2103115-4-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Anil Samal
Jakub Kicinski
parent
ac21add254
commit
70838938e8
@ -1461,6 +1461,55 @@ struct ice_aqc_get_sensor_reading_resp {
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} data;
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};
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/* DNL call command (indirect 0x0682)
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* Struct is used for both command and response
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*/
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struct ice_aqc_dnl_call_command {
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u8 ctx; /* Used in command, reserved in response */
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u8 reserved;
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__le16 activity_id;
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#define ICE_AQC_ACT_ID_DNL 0x1129
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__le32 reserved1;
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__le32 addr_high;
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__le32 addr_low;
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};
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struct ice_aqc_dnl_equa_param {
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__le16 data_in;
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#define ICE_AQC_RX_EQU_SHIFT 8
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#define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT)
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#define ICE_AQC_TX_EQU_PRE1 0x0
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#define ICE_AQC_TX_EQU_PRE3 0x3
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#define ICE_AQC_TX_EQU_ATTEN 0x4
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#define ICE_AQC_TX_EQU_POST1 0x8
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#define ICE_AQC_TX_EQU_PRE2 0xC
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__le16 op_code_serdes_sel;
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#define ICE_AQC_OP_CODE_SHIFT 4
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#define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT)
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#define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT)
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__le32 reserved[3];
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};
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struct ice_aqc_dnl_equa_respon {
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/* Equalization value can be negative */
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int val;
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__le32 reserved[3];
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};
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/* DNL call command/response buffer (indirect 0x0682) */
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struct ice_aqc_dnl_call {
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union {
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struct ice_aqc_dnl_equa_param txrx_equa_reqs;
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__le32 stores[4];
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struct ice_aqc_dnl_equa_respon txrx_equa_resp;
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} sto;
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};
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struct ice_aqc_link_topo_params {
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u8 lport_num;
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u8 lport_num_valid;
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@ -2564,6 +2613,7 @@ struct ice_aq_desc {
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struct ice_aqc_get_link_status get_link_status;
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struct ice_aqc_event_lan_overflow lan_overflow;
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struct ice_aqc_get_link_topo get_link_topo;
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struct ice_aqc_dnl_call_command dnl_call;
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struct ice_aqc_i2c read_write_i2c;
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struct ice_aqc_read_i2c_resp read_i2c_resp;
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struct ice_aqc_get_set_tx_topo get_set_tx_topo;
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@ -2688,6 +2738,7 @@ enum ice_adminq_opc {
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ice_aqc_opc_set_phy_rec_clk_out = 0x0630,
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ice_aqc_opc_get_phy_rec_clk_out = 0x0631,
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ice_aqc_opc_get_sensor_reading = 0x0632,
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ice_aqc_opc_dnl_call = 0x0682,
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ice_aqc_opc_get_link_topo = 0x06E0,
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ice_aqc_opc_read_i2c = 0x06E2,
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ice_aqc_opc_write_i2c = 0x06E3,
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@ -3371,6 +3371,43 @@ int ice_update_link_info(struct ice_port_info *pi)
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return status;
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}
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/**
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* ice_aq_get_phy_equalization - function to read serdes equaliser
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* value from firmware using admin queue command.
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* @hw: pointer to the HW struct
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* @data_in: represents the serdes equalization parameter requested
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* @op_code: represents the serdes number and flag to represent tx or rx
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* @serdes_num: represents the serdes number
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* @output: pointer to the caller-supplied buffer to return serdes equaliser
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*
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* Return: non-zero status on error and 0 on success.
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*/
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int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
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u8 serdes_num, int *output)
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{
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struct ice_aqc_dnl_call_command *cmd;
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struct ice_aqc_dnl_call buf = {};
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struct ice_aq_desc desc;
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int err;
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buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in);
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buf.sto.txrx_equa_reqs.op_code_serdes_sel =
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cpu_to_le16(op_code | (serdes_num & 0xF));
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cmd = &desc.params.dnl_call;
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ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call);
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desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF |
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ICE_AQ_FLAG_RD |
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ICE_AQ_FLAG_SI);
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desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call));
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cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL);
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err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call),
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NULL);
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*output = err ? 0 : buf.sto.txrx_equa_resp.val;
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return err;
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}
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#define FEC_REG_PORT(port) { \
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FEC_CORR_LOW_REG_PORT##port, \
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FEC_CORR_HIGH_REG_PORT##port, \
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@ -142,6 +142,8 @@ int
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ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
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struct ice_port_info *pi);
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bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
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int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
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u8 serdes_num, int *output);
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int
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ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
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enum ice_fec_stats_types fec_type, u32 *output);
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@ -463,7 +463,8 @@ ice_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
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static int ice_get_regs_len(struct net_device __always_unused *netdev)
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{
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return sizeof(ice_regs_dump_list);
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return (sizeof(ice_regs_dump_list) +
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sizeof(struct ice_regdump_to_ethtool));
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}
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/**
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@ -681,6 +682,137 @@ static int ice_get_port_topology(struct ice_hw *hw, u8 lport,
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return 0;
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}
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/**
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* ice_get_tx_rx_equa - read serdes tx rx equaliser param
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* @hw: pointer to the HW struct
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* @serdes_num: represents the serdes number
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* @ptr: structure to read all serdes parameter for given serdes
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*
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* Return: all serdes equalization parameter supported per serdes number
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*/
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static int ice_get_tx_rx_equa(struct ice_hw *hw, u8 serdes_num,
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struct ice_serdes_equalization_to_ethtool *ptr)
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{
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int err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_TX_EQU_PRE1,
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ICE_AQC_OP_CODE_TX_EQU, serdes_num,
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&ptr->tx_equalization_pre1);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_TX_EQU_PRE3,
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ICE_AQC_OP_CODE_TX_EQU, serdes_num,
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&ptr->tx_equalization_pre3);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_TX_EQU_ATTEN,
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ICE_AQC_OP_CODE_TX_EQU, serdes_num,
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&ptr->tx_equalization_atten);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_TX_EQU_POST1,
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ICE_AQC_OP_CODE_TX_EQU, serdes_num,
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&ptr->tx_equalization_post1);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_TX_EQU_PRE2,
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ICE_AQC_OP_CODE_TX_EQU, serdes_num,
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&ptr->tx_equalization_pre2);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_PRE2,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_pre2);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_PRE1,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_pre1);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_POST1,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_post1);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_BFLF,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_bflf);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_BFHF,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_bfhf);
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if (err)
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return err;
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err = ice_aq_get_phy_equalization(hw, ICE_AQC_RX_EQU_DRATE,
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ICE_AQC_OP_CODE_RX_EQU, serdes_num,
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&ptr->rx_equalization_drate);
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if (err)
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return err;
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return 0;
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}
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/**
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* ice_get_extended_regs - returns FEC correctable, uncorrectable stats per
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* pcsquad, pcsport
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* @netdev: pointer to net device structure
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* @p: output buffer to fill requested register dump
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*
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* Return: 0 on success, negative on failure.
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*/
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static int ice_get_extended_regs(struct net_device *netdev, void *p)
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{
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struct ice_netdev_priv *np = netdev_priv(netdev);
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struct ice_regdump_to_ethtool *ice_prv_regs_buf;
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struct ice_port_topology port_topology = {};
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struct ice_port_info *pi;
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struct ice_pf *pf;
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struct ice_hw *hw;
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unsigned int i;
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int err;
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pf = np->vsi->back;
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hw = &pf->hw;
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pi = np->vsi->port_info;
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/* Serdes parameters are not supported if not the PF VSI */
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if (np->vsi->type != ICE_VSI_PF || !pi)
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return -EINVAL;
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err = ice_get_port_topology(hw, pi->lport, &port_topology);
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if (err)
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return -EINVAL;
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if (port_topology.serdes_lane_count > 4)
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return -EINVAL;
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ice_prv_regs_buf = p;
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/* Get serdes equalization parameter for available serdes */
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for (i = 0; i < port_topology.serdes_lane_count; i++) {
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u8 serdes_num = 0;
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serdes_num = port_topology.primary_serdes_lane + i;
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err = ice_get_tx_rx_equa(hw, serdes_num,
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&ice_prv_regs_buf->equalization[i]);
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if (err)
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return -EINVAL;
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}
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return 0;
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}
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static void
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ice_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
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{
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@ -690,10 +822,12 @@ ice_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
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u32 *regs_buf = (u32 *)p;
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unsigned int i;
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regs->version = 1;
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regs->version = 2;
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for (i = 0; i < ARRAY_SIZE(ice_regs_dump_list); ++i)
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regs_buf[i] = rd32(hw, ice_regs_dump_list[i]);
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ice_get_extended_regs(netdev, (void *)®s_buf[i]);
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}
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static u32 ice_get_msglevel(struct net_device *netdev)
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@ -9,6 +9,25 @@ struct ice_phy_type_to_ethtool {
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u8 link_mode;
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};
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struct ice_serdes_equalization_to_ethtool {
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int rx_equalization_pre2;
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int rx_equalization_pre1;
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int rx_equalization_post1;
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int rx_equalization_bflf;
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int rx_equalization_bfhf;
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int rx_equalization_drate;
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int tx_equalization_pre1;
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int tx_equalization_pre3;
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int tx_equalization_atten;
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int tx_equalization_post1;
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int tx_equalization_pre2;
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};
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struct ice_regdump_to_ethtool {
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/* A multilane port can have max 4 serdes */
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struct ice_serdes_equalization_to_ethtool equalization[4];
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};
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/* Port topology from lport i.e.
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* serdes mapping, pcsquad, macport, cage etc...
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*/
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