msm: gpio: Add irq support to v2 gpiolib.
Complete the MSM v2 gpio subsystem by adding irq_chip. Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
This commit is contained in:
Gregory Bean
Daniel Walker
parent
0cc2fc1f2f
commit
70cc2c00d7
@ -15,7 +15,13 @@
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* 02110-1301, USA.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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@ -27,29 +33,103 @@
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/* Bits of interest in the GPIO_IN_OUT register.
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*/
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enum {
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GPIO_IN_BIT = 0,
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GPIO_OUT_BIT = 1
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GPIO_IN = 0,
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GPIO_OUT = 1
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};
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/* Bits of interest in the GPIO_INTR_STATUS register.
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*/
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enum {
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INTR_STATUS = 0,
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};
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/* Bits of interest in the GPIO_CFG register.
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*/
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enum {
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GPIO_OE_BIT = 9,
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GPIO_OE = 9,
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};
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/* Bits of interest in the GPIO_INTR_CFG register.
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* When a GPIO triggers, two separate decisions are made, controlled
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* by two separate flags.
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*
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* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
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* register for that GPIO will be updated to reflect the triggering of that
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* gpio. If this bit is 0, this register will not be updated.
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* - Second, INTR_ENABLE controls whether an interrupt is triggered.
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*
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* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
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* can be triggered but the status register will not reflect it.
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*/
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enum {
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INTR_ENABLE = 0,
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INTR_POL_CTL = 1,
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INTR_DECT_CTL = 2,
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INTR_RAW_STATUS_EN = 3,
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};
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/* Codes of interest in GPIO_INTR_CFG_SU.
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*/
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enum {
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TARGET_PROC_SCORPION = 4,
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TARGET_PROC_NONE = 7,
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};
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#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
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#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
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#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
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#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
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#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
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/**
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* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
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*
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* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
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* keeping track of which gpios are unmasked as irq sources, we avoid
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* having to do readl calls on hundreds of iomapped registers each time
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* the summary interrupt fires in order to locate the active interrupts.
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*
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* @wake_irqs: a bitmap for tracking which interrupt lines are enabled
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* as wakeup sources. When the device is suspended, interrupts which are
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* not wakeup sources are disabled.
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*
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* @dual_edge_irqs: a bitmap used to track which irqs are configured
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* as dual-edge, as this is not supported by the hardware and requires
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* some special handling in the driver.
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*/
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struct msm_gpio_dev {
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struct gpio_chip gpio_chip;
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DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
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DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
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DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
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};
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static DEFINE_SPINLOCK(tlmm_lock);
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static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
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{
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return container_of(chip, struct msm_gpio_dev, gpio_chip);
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}
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static inline void set_gpio_bits(unsigned n, void __iomem *reg)
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{
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writel(readl(reg) | n, reg);
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}
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static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
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{
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writel(readl(reg) & ~n, reg);
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}
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static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN_BIT);
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return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
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}
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static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset));
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writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
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}
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static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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@ -57,8 +137,7 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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unsigned long irq_flags;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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writel(readl(GPIO_CONFIG(offset)) & ~BIT(GPIO_OE_BIT),
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GPIO_CONFIG(offset));
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clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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@ -71,8 +150,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip,
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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msm_gpio_set(chip, offset, val);
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writel(readl(GPIO_CONFIG(offset)) | BIT(GPIO_OE_BIT),
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GPIO_CONFIG(offset));
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set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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@ -87,30 +165,215 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
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msm_gpiomux_put(chip->base + offset);
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}
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static struct gpio_chip msm_gpio = {
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.base = 0,
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.ngpio = NR_GPIO_IRQS,
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.direction_input = msm_gpio_direction_input,
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.direction_output = msm_gpio_direction_output,
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.get = msm_gpio_get,
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.set = msm_gpio_set,
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.request = msm_gpio_request,
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.free = msm_gpio_free,
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static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return MSM_GPIO_TO_INT(chip->base + offset);
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}
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static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
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{
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return irq - MSM_GPIO_TO_INT(chip->base);
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}
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static struct msm_gpio_dev msm_gpio = {
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.gpio_chip = {
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.base = 0,
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.ngpio = NR_GPIO_IRQS,
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.direction_input = msm_gpio_direction_input,
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.direction_output = msm_gpio_direction_output,
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.get = msm_gpio_get,
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.set = msm_gpio_set,
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.to_irq = msm_gpio_to_irq,
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.request = msm_gpio_request,
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.free = msm_gpio_free,
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},
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};
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/* For dual-edge interrupts in software, since the hardware has no
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* such support:
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*
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* At appropriate moments, this function may be called to flip the polarity
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* settings of both-edge irq lines to try and catch the next edge.
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*
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* The attempt is considered successful if:
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* - the status bit goes high, indicating that an edge was caught, or
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* - the input value of the gpio doesn't change during the attempt.
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* If the value changes twice during the process, that would cause the first
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* test to fail but would force the second, as two opposite
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* transitions would cause a detection no matter the polarity setting.
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*
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* The do-loop tries to sledge-hammer closed the timing hole between
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* the initial value-read and the polarity-write - if the line value changes
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* during that window, an interrupt is lost, the new polarity setting is
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* incorrect, and the first success test will fail, causing a retry.
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*
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* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
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*/
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static void msm_gpio_update_dual_edge_pos(unsigned gpio)
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{
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int loop_limit = 100;
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unsigned val, val2, intstat;
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do {
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val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
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if (val)
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clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
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else
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set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
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val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
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intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
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if (intstat || val == val2)
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return;
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} while (loop_limit-- > 0);
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pr_err("dual-edge irq failed to stabilize, "
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"interrupts dropped. %#08x != %#08x\n",
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val, val2);
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}
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static void msm_gpio_irq_ack(unsigned int irq)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
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writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
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if (test_bit(gpio, msm_gpio.dual_edge_irqs))
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msm_gpio_update_dual_edge_pos(gpio);
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}
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static void msm_gpio_irq_mask(unsigned int irq)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
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unsigned long irq_flags;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
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clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
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__clear_bit(gpio, msm_gpio.enabled_irqs);
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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}
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static void msm_gpio_irq_unmask(unsigned int irq)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
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unsigned long irq_flags;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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__set_bit(gpio, msm_gpio.enabled_irqs);
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set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
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writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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}
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static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
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unsigned long irq_flags;
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uint32_t bits;
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spin_lock_irqsave(&tlmm_lock, irq_flags);
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bits = readl(GPIO_INTR_CFG(gpio));
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if (flow_type & IRQ_TYPE_EDGE_BOTH) {
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bits |= BIT(INTR_DECT_CTL);
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irq_desc[irq].handle_irq = handle_edge_irq;
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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__set_bit(gpio, msm_gpio.dual_edge_irqs);
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else
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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} else {
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bits &= ~BIT(INTR_DECT_CTL);
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irq_desc[irq].handle_irq = handle_level_irq;
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__clear_bit(gpio, msm_gpio.dual_edge_irqs);
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}
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if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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bits |= BIT(INTR_POL_CTL);
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else
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bits &= ~BIT(INTR_POL_CTL);
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writel(bits, GPIO_INTR_CFG(gpio));
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if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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msm_gpio_update_dual_edge_pos(gpio);
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spin_unlock_irqrestore(&tlmm_lock, irq_flags);
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return 0;
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}
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/*
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* When the summary IRQ is raised, any number of GPIO lines may be high.
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* It is the job of the summary handler to find all those GPIO lines
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* which have been set as summary IRQ lines and which are triggered,
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* and to call their interrupt handlers.
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*/
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static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long i;
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for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
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i < NR_GPIO_IRQS;
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i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
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if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
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generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
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i));
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}
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desc->chip->ack(irq);
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}
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static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
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{
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
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if (on) {
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if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
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set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
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set_bit(gpio, msm_gpio.wake_irqs);
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} else {
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clear_bit(gpio, msm_gpio.wake_irqs);
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if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
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set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
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}
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return 0;
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}
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static struct irq_chip msm_gpio_irq_chip = {
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.name = "msmgpio",
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.mask = msm_gpio_irq_mask,
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.unmask = msm_gpio_irq_unmask,
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.ack = msm_gpio_irq_ack,
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.set_type = msm_gpio_irq_set_type,
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.set_wake = msm_gpio_irq_set_wake,
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};
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static int __devinit msm_gpio_probe(struct platform_device *dev)
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{
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int ret;
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int i, irq, ret;
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msm_gpio.label = dev->name;
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ret = gpiochip_add(&msm_gpio);
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bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
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bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
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bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
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msm_gpio.gpio_chip.label = dev->name;
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ret = gpiochip_add(&msm_gpio.gpio_chip);
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if (ret < 0)
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return ret;
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return ret;
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for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
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irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
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set_irq_chip(irq, &msm_gpio_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
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msm_summary_irq_handler);
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return 0;
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}
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static int __devexit msm_gpio_remove(struct platform_device *dev)
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{
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int ret = gpiochip_remove(&msm_gpio);
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int ret = gpiochip_remove(&msm_gpio.gpio_chip);
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if (ret < 0)
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return ret;
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