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coresight: document the bindings for the ATCLK

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Put in a blurb in the device tree bindings indicating that
coresight blocks may have an optional ATCLK.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Linus Walleij 2015-05-19 10:55:19 -06:00 committed by Greg Kroah-Hartman
parent 9875cd9ce2
commit 70dd9d2f0a
1 changed files with 7 additions and 4 deletions
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11
Documentation/devicetree/bindings/arm/coresight.txt
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@ -21,11 +21,14 @@ its hardware characteristcs.
* reg: physical base address and length of the register
set(s) of the component.
* clocks: the clock associated to this component.
* clocks: the clocks associated to this component.
* clock-names: the name of the clock as referenced by the code.
Since we are using the AMBA framework, the name should be
"apb_pclk".
* clock-names: the name of the clocks referenced by the code.
Since we are using the AMBA framework, the name of the clock
providing the interconnect should be "apb_pclk", and some
coresight blocks also have an additional clock "atclk", which
clocks the core of that coresight component. The latter clock
is optional.
* port or ports: The representation of the component's port
layout using the generic DT graph presentation found in