LoongArch: Remove clock setting during cpu hotplug stage
On physical machine we can save power by disabling clock of hot removed cpu. However as different platforms require different methods to configure clocks, the code is platform-specific, and probably belongs to firmware/pmu or cpu regulator, rather than generic arch/loongarch code. Also, there is no such register on QEMU virt machine since the clock/frequency regulation is not emulated. This patch removes the hard-coded clock register accesses in generic LoongArch cpu hotplug flow. Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Bibo Mao
Huacai Chen
parent
f62b7626cb
commit
71610ab1d0
@ -278,116 +278,29 @@ void loongson3_cpu_die(unsigned int cpu)
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mb();
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mb();
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}
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}
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/*
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void play_dead(void)
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* The target CPU should go to XKPRANGE (uncached area) and flush
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* ICache/DCache/VCache before the control CPU can safely disable its clock.
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*/
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static void loongson3_play_dead(int *state_addr)
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{
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{
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register int val;
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register uint64_t addr;
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register void *addr;
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register void (*init_fn)(void);
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register void (*init_fn)(void);
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__asm__ __volatile__(
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idle_task_exit();
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" li.d %[addr], 0x8000000000000000\n"
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"1: cacop 0x8, %[addr], 0 \n" /* flush ICache */
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" cacop 0x8, %[addr], 1 \n"
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" cacop 0x8, %[addr], 2 \n"
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" cacop 0x8, %[addr], 3 \n"
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" cacop 0x9, %[addr], 0 \n" /* flush DCache */
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" cacop 0x9, %[addr], 1 \n"
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" cacop 0x9, %[addr], 2 \n"
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" cacop 0x9, %[addr], 3 \n"
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" addi.w %[sets], %[sets], -1 \n"
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" addi.d %[addr], %[addr], 0x40 \n"
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" bnez %[sets], 1b \n"
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" li.d %[addr], 0x8000000000000000\n"
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"2: cacop 0xa, %[addr], 0 \n" /* flush VCache */
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" cacop 0xa, %[addr], 1 \n"
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" cacop 0xa, %[addr], 2 \n"
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" cacop 0xa, %[addr], 3 \n"
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" cacop 0xa, %[addr], 4 \n"
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" cacop 0xa, %[addr], 5 \n"
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" cacop 0xa, %[addr], 6 \n"
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" cacop 0xa, %[addr], 7 \n"
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" cacop 0xa, %[addr], 8 \n"
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" cacop 0xa, %[addr], 9 \n"
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" cacop 0xa, %[addr], 10 \n"
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" cacop 0xa, %[addr], 11 \n"
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" cacop 0xa, %[addr], 12 \n"
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" cacop 0xa, %[addr], 13 \n"
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" cacop 0xa, %[addr], 14 \n"
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" cacop 0xa, %[addr], 15 \n"
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" addi.w %[vsets], %[vsets], -1 \n"
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" addi.d %[addr], %[addr], 0x40 \n"
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" bnez %[vsets], 2b \n"
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" li.w %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
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" st.w %[val], %[state_addr], 0 \n"
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" dbar 0 \n"
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" cacop 0x11, %[state_addr], 0 \n" /* flush entry of *state_addr */
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: [addr] "=&r" (addr), [val] "=&r" (val)
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: [state_addr] "r" (state_addr),
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[sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
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[vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
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local_irq_enable();
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local_irq_enable();
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change_csr_ecfg(ECFG0_IM, ECFGF_IPI);
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set_csr_ecfg(ECFGF_IPI);
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__this_cpu_write(cpu_state, CPU_DEAD);
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__asm__ __volatile__(
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__smp_mb();
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" idle 0 \n"
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do {
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" li.w $t0, 0x1020 \n"
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__asm__ __volatile__("idle 0\n\t");
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" iocsrrd.d %[init_fn], $t0 \n" /* Get init PC */
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addr = iocsr_read64(LOONGARCH_IOCSR_MBUF0);
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: [init_fn] "=&r" (addr)
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} while (addr == 0);
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: /* No Input */
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: "a0");
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init_fn = (void *)TO_CACHE(addr);
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init_fn = __va(addr);
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iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_CLEAR);
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init_fn();
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init_fn();
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unreachable();
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unreachable();
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}
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}
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void play_dead(void)
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{
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int *state_addr;
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unsigned int cpu = smp_processor_id();
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void (*play_dead_uncached)(int *s);
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idle_task_exit();
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play_dead_uncached = (void *)TO_UNCACHE(__pa((unsigned long)loongson3_play_dead));
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state_addr = &per_cpu(cpu_state, cpu);
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mb();
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play_dead_uncached(state_addr);
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}
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static int loongson3_enable_clock(unsigned int cpu)
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{
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uint64_t core_id = cpu_data[cpu].core;
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uint64_t package_id = cpu_data[cpu].package;
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LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
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return 0;
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}
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static int loongson3_disable_clock(unsigned int cpu)
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{
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uint64_t core_id = cpu_data[cpu].core;
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uint64_t package_id = cpu_data[cpu].package;
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LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
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return 0;
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}
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static int register_loongson3_notifier(void)
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{
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return cpuhp_setup_state_nocalls(CPUHP_LOONGARCH_SOC_PREPARE,
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"loongarch/loongson:prepare",
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loongson3_enable_clock,
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loongson3_disable_clock);
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}
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early_initcall(register_loongson3_notifier);
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#endif
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#endif
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/*
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/*
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@ -130,7 +130,6 @@ enum cpuhp_state {
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CPUHP_ZCOMP_PREPARE,
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CPUHP_ZCOMP_PREPARE,
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CPUHP_TIMERS_PREPARE,
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CPUHP_TIMERS_PREPARE,
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CPUHP_MIPS_SOC_PREPARE,
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CPUHP_MIPS_SOC_PREPARE,
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CPUHP_LOONGARCH_SOC_PREPARE,
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CPUHP_BP_PREPARE_DYN,
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CPUHP_BP_PREPARE_DYN,
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CPUHP_BP_PREPARE_DYN_END = CPUHP_BP_PREPARE_DYN + 20,
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CPUHP_BP_PREPARE_DYN_END = CPUHP_BP_PREPARE_DYN + 20,
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CPUHP_BRINGUP_CPU,
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CPUHP_BRINGUP_CPU,
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