iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

More Qualcomm ARM64 Devicetree updated for v6.4

Browse Source 
Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1
 board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on
 IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support
 for Xiaomi Mi A3 is introduced on SM6125.
 
 Support for the output-enable/disable flag is introduced in the
 pinctrl-msm driver, and the non-standard "input-enable" is dropped from
 a range of platforms.
 
 A wide range of smaller fixes are introduced, based on Devicetree
 validation.
 
 MSM8953 gains LPASS, MPSS and Wireless subsystem support.
 
 The iommus property is removed from PCIe nodes in all platforms, as the
 only the child devices should be associated with iommu groups, through
 the existing iommu-map property.
 
 A few QUP instances are introduced on the IPQ5332 platform, and support
 for the MI01.6 board is introduced.
 
 The reserved-memory map on Huawei Nexus 6P is updated with the addition
 of splash screen framebuffer memory and adjustment to the reserved
 memory region overlapping the smem region.
 
 Regulators are introduces for the SA8775P Ride platform.
 
 A regulator is marked always-on, for correctness, on Trogdor. Pinconf
 fixes are introduced to both sc7180 and sc7280 devices. A dedicated
 reviewers list is added for boards relevant to the Chromebook engineers.
 
 A set of pinconf fixes are introduced for sc8280xp, labels are
 introduced for Soundwire nodes.
 
 The sensor core remoteproc and FastRPC thereon, is introduce in SDM845
 and enabled for OnePlus 6/6T and Shift Shift6mq.
 
 RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab
 P11.
 
 UFS support is introduced on SM6125.
 
 SM8150 no longer defines the GPU to be in headless mode by default, GPU
 speedbins are introduced.
 
 GPU speedbins are introduced for SM8250 as well, as is support for
 display on Xiaomi Mi Pad 5 Pro, with two different panels supported.
 
 Soundwire controllers, ADSP audio codec macros and the Inline Crypto
 Engine support is added to the SM8550 platform.
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmQ4xScVHGFuZGVyc3Nv
 bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FyAEQANkYPPmcATVeCMu8ABqOGr2YpN2v
 d1e8/Kdtrg0qWtqnXgkcec/+HvOqxTYlqW/iYLGf2fkgheQhbY8YOv3AU7FEG9Jr
 RNsPiyZ/2o2VPcskS6jQSsbAGKaWbhSh7Ao2lSUNSsPuhHOYw/Nu3iRxKCE1FdHn
 yqF2b+cipMwogKgx4LFCLwRTAG6f9HumDb3dwLeiUFPZH321MeJu8FzHnLt/wU5Z
 64EzST7W2J5PlWdFEoJOXGDmxnM35hKJrzliRf5oqTHhUMUlyxQI6W61vSfsz5PP
 7AE8DEMHD9b5fbRUf2mcMffPmhdvL194dSx10eTFMEuyoe+19CaMiZV86Cf8HeZ7
 8K6ZZJ/tF/UrOBc7zMDtCUTm5f9MYyfiKqQNJekcpYWugQSsKw8TQZ58q4jM352R
 vvq2ywMDk2olt4Jn0on7L6M8x+uOGIMQG3B32jJijE0fRFdMcHJMwfxEBsrGmsUW
 vZvDdhQtIQSy6aLHFqwzFbGePq1GeYLjEh+PbT8EHkaCHFx0dA+EobLnwcyqJYky
 AmWA2wjbIYU96KahSZ4Sz3MWTy9MrhHa10bwWoBvOsp1AAM/gpx5nIgoHXmzp2pg
 cXgCqzUBgdMrWfjEFgtLY1HyRMGbQ7T+fQhaS5xn9TnHNqnvqLAW/APhyhrAWWXx
 475V7NXAQMDd5FQX
 =vVPv
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5eO4ACgkQYKtH/8kJ
 UifICRAAz4I3XrqaTmlk8HtHwCSxhQfpF/6B+HmFbRG/tNFzWu4rbCyju2Gja6bi
 lQDxP42uuH78m35rXtAA848bZ8BpUQesJcGuwQoPYRwCPTLZH493QryEZ2DM4rp1
 IjKe1FmuHlToBiPxBgk+3EqaulXM9wSvV6lb7HlsEx6vt8TC9i0IhnfD6jHJ7ESs
 Pln0nmTREAyNpdcGOfmCZ3m4Rc6rvz8WHu+pX/nYZIdF44txYJaVh4mU7T0DuxUo
 KF2rfpPko4FXxqN6V3fYBRuRihu9lAqPwg86imQruqHnc0Lrfw2IMAdnUtXcmJOo
 qrYvQgifJKd5TZ1aYrkiQk5jSA9Wy5Wt66rzu7XGC8XhEftYcs3D/gYkqfRifI+a
 d+dqYLYXOLTopdDRfGgnCa74cNs7A+Y/mUC+WZQmWFI4q7I9SUnipRfzZt44Vbmp
 mn1C6XIoeseO8HOHDx0dNUsgiDH/JDLZv1/RTT6fWj3+9R2fQKmtdq8i9ZBdKL7r
 M/bAsS8PENmV6Dv3bHWxIa4xC380bDgCrjsLdHh5Oqfvbv2NHpftHkOaCK8BgE/t
 8YubTKxaxw0YQ0NtI+ku6Km9VJCG1zDEiQPMYEcklEzUj09CfkfCqBg4EkI92u2i
 P215llOlgIUzAgad/S0H2YhIIdnhsacU4adPEDD3devtKWdH+PE=
 =HFrk
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

More Qualcomm ARM64 Devicetree updated for v6.4

Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1
board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on
IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support
for Xiaomi Mi A3 is introduced on SM6125.

Support for the output-enable/disable flag is introduced in the
pinctrl-msm driver, and the non-standard "input-enable" is dropped from
a range of platforms.

A wide range of smaller fixes are introduced, based on Devicetree
validation.

MSM8953 gains LPASS, MPSS and Wireless subsystem support.

The iommus property is removed from PCIe nodes in all platforms, as the
only the child devices should be associated with iommu groups, through
the existing iommu-map property.

A few QUP instances are introduced on the IPQ5332 platform, and support
for the MI01.6 board is introduced.

The reserved-memory map on Huawei Nexus 6P is updated with the addition
of splash screen framebuffer memory and adjustment to the reserved
memory region overlapping the smem region.

Regulators are introduces for the SA8775P Ride platform.

A regulator is marked always-on, for correctness, on Trogdor. Pinconf
fixes are introduced to both sc7180 and sc7280 devices. A dedicated
reviewers list is added for boards relevant to the Chromebook engineers.

A set of pinconf fixes are introduced for sc8280xp, labels are
introduced for Soundwire nodes.

The sensor core remoteproc and FastRPC thereon, is introduce in SDM845
and enabled for OnePlus 6/6T and Shift Shift6mq.

RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab
P11.

UFS support is introduced on SM6125.

SM8150 no longer defines the GPU to be in headless mode by default, GPU
speedbins are introduced.

GPU speedbins are introduced for SM8250 as well, as is support for
display on Xiaomi Mi Pad 5 Pro, with two different panels supported.

Soundwire controllers, ADSP audio codec macros and the Inline Crypto
Engine support is added to the SM8550 platform.

* tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits)
  arm64: dts: qcom: Add base qrb4210-rb2 board dts
  arm64: dts: qcom: sm8550: add Soundwire controllers
  arm64: dts: qcom: sm8250: Add GPU speedbin support
  arm64: dts: qcom: sm8150: Add GPU speedbin support
  arm64: dts: qcom: sm8150: Don't start Adreno in headless mode
  arm64: dts: qcom: ipq5332: add support for the RDP468 variant
  arm64: dts: qcom: sdm630: move DSI opp-table out of DSI node
  arm64: dts: qcom: sm6115p-j606f: Enable ATH10K WiFi
  arm64: dts: qcom: sm6115p-j606f: Enable remoteprocs
  arm64: dts: qcom: sm6115: Add RMTFS
  arm64: dts: qcom: sm6115-j606f: Add ramoops node
  arm64: dts: qcom: msm8916-thwc-ufi001c: add function to pin config
  arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
  arm64: dts: MSM8953: Add lpass nodes
  arm64: dts: MSM8953: Add mpss nodes
  arm64: dts: MSM8953: Add wcnss nodes
  arm64: dts: qcom: sm8350: remove superfluous "input-enable"
  arm64: dts: qcom: sm8150: remove superfluous "input-enable"
  arm64: dts: qcom: apq8016: remove superfluous "input-enable"
  arm64: dts: qcom: sc8280xp-lenovo-thinkpad: correct pin drive-strength
  ...

Link: https://lore.kernel.org/r/20230414031550.2412379-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 18:00:39 +02:00
commit 718acce6f0
75 changed files with 4863 additions and 203 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml Normal file
View File

@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ9574
maintainers:
- Anusha Rao <quic_anusha@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ9574
See also::
include/dt-bindings/clock/qcom,ipq9574-gcc.h
include/dt-bindings/reset/qcom,ipq9574-gcc.h
properties:
compatible:
const: qcom,ipq9574-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Bias PLL ubi clock source
- description: PCIE30 PHY0 pipe clock source
- description: PCIE30 PHY1 pipe clock source
- description: PCIE30 PHY2 pipe clock source
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq9574-gcc";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&bias_pll_ubi_nc_clk>,
<&pcie30_phy0_pipe_clk>,
<&pcie30_phy1_pipe_clk>,
<&pcie30_phy2_pipe_clk>,
<&pcie30_phy3_pipe_clk>,
<&usb3phy_0_cc_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
View File

@ -75,7 +75,9 @@ $defs:
bias-pull-down: true
bias-pull-up: true
bias-disable: true
input-enable: true
input-enable: false
output-disable: true
output-enable: true
output-high: true
output-low: true

6
MAINTAINERS
View File

@ -2604,6 +2604,12 @@ F: include/dt-bindings/*/qcom*
F: include/linux/*/qcom*
F: include/linux/soc/qcom/
ARM/QUALCOMM CHROMEBOOK SUPPORT
R: cros-qcom-dts-watchers@chromium.org
F: arch/arm64/boot/dts/qcom/sc7180*
F: arch/arm64/boot/dts/qcom/sc7280*
F: arch/arm64/boot/dts/qcom/sdm845-cheza*
ARM/RDA MICRO ARCHITECTURE
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

8
arch/arm64/boot/dts/qcom/Makefile
View File

@ -4,10 +4,12 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
@ -71,6 +73,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
@ -172,6 +176,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
@ -184,7 +189,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb

2
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@ -729,7 +729,6 @@
function = "gpio";
drive-strength = <8>;
input-enable;
bias-pull-up;
};
@ -770,7 +769,6 @@
function = "gpio";
drive-strength = <8>;
input-enable;
bias-pull-up;
};
};

14
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
View File

@ -28,6 +28,13 @@
status = "okay";
};
&blsp1_i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhc {
bus-width = <4>;
max-frequency = <192000000>;
@ -50,6 +57,13 @@
/* PINCTRL */
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";
function = "blsp1_i2c0";
drive-strength = <8>;
bias-pull-up;
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";

103
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts Normal file
View File

@ -0,0 +1,103 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 RDP468 board device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ipq5332.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_spi0 {
pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
};
};
&sdhc {
bus-width = <4>;
max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio12";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
spi_0_data_clk_pins: spi-0-data-clk-state {
pins = "gpio14", "gpio15", "gpio16";
function = "blsp0_spi";
drive-strength = <2>;
bias-pull-down;
};
spi_0_cs_pins: spi-0-cs-state {
pins = "gpio17";
function = "blsp0_spi";
drive-strength = <2>;
bias-pull-up;
};
};

67
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -134,6 +134,13 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
rng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
@ -191,6 +198,16 @@
status = "disabled";
};
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x1d000>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart0: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
@ -201,6 +218,48 @@
status = "disabled";
};
blsp1_spi0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_spi2: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "tx", "rx";
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@ -233,6 +292,14 @@
};
};
watchdog: watchdog@b017000 {
compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
reg = <0x0b017000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
timeout-sec = <30>;
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq5332-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";

3
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -686,7 +686,8 @@
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";

84
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ9574 AL02-C7 board device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ipq9574.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&blsp1_uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};
&xo_board_clk {
clock-frequency = <24000000>;
};

270
arch/arm64/boot/dts/qcom/ipq9574.dtsi Normal file
View File

@ -0,0 +1,270 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ9574 SoC device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
compatible = "fixed-clock";
clock-frequency = <353000000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
memory@40000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x40000000 0x0 0x0>;
};
pmu {
compatible = "arm,cortex-a73-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz_region: tz@4a600000 {
reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq9574-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 65>;
interrupt-controller;
#interrupt-cells = <2>;
uart2_pins: uart2-state {
pins = "gpio34", "gpio35";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq9574-gcc";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&bias_pll_ubi_nc_clk>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board_clk>;
clock-names = "iface", "core", "xo";
non-removable;
status = "disabled";
};
blsp1_uart2: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b1000 0x200>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
<0x0b002000 0x1000>, /* GICC */
<0x0b001000 0x1000>, /* GICH */
<0x0b004000 0x1000>; /* GICV */
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0 0x0b00c000 0x3000>;
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
reg = <0x00000000 0xffd>;
msi-controller;
};
v2m1: v2m@1000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00001000 0xffd>;
msi-controller;
};
v2m2: v2m@2000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00002000 0xffd>;
msi-controller;
};
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@b120000 {
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
frame@b123000 {
reg = <0x0b123000 0x1000>;
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@b124000 {
reg = <0x0b124000 0x1000>;
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@b125000 {
reg = <0x0b125000 0x1000>;
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@b126000 {
reg = <0x0b126000 0x1000>;
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@b127000 {
reg = <0x0b127000 0x1000>;
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@b128000 {
reg = <0x0b128000 0x1000>;
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

3
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
View File

@ -44,18 +44,21 @@
sim_ctrl_default: sim-ctrl-default-state {
esim-sel-pins {
pins = "gpio0", "gpio3";
function = "gpio";
bias-disable;
output-low;
};
sim-en-pins {
pins = "gpio1";
function = "gpio";
bias-disable;
output-low;
};
sim-sel-pins {
pins = "gpio2";
function = "gpio";
bias-disable;
output-high;
};

358
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -6,6 +6,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -326,6 +329,80 @@
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-wcnss {
compatible = "qcom,smp2p";
qcom,smem = <451>, <431>;
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
smp2p_wcnss_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_wcnss_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smsm {
compatible = "qcom,smsm";
@ -340,6 +417,22 @@
#qcom,smem-state-cells = <1>;
};
modem_smsm: modem@1 {
reg = <1>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
wcnss_smsm: wcnss@6 {
reg = <6>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
@ -630,6 +723,37 @@
drive-strength = <2>;
bias-disable;
};
wcnss_pin_a: wcnss-active-state {
wcss-wlan2-pins {
pins = "gpio76";
function = "wcss_wlan2";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan1-pins {
pins = "gpio77";
function = "wcss_wlan1";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan0-pins {
pins = "gpio78";
function = "wcss_wlan0";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan-pins {
pins = "gpio79", "gpio80";
function = "wcss_wlan";
drive-strength = <6>;
bias-pull-up;
};
};
};
gcc: clock-controller@1800000 {
@ -931,6 +1055,60 @@
#size-cells = <0>;
};
mpss: remoteproc@4080000 {
compatible = "qcom,msm8953-mss-pil";
reg = <0x04080000 0x100>,
<0x04020000 0x040>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
power-domains = <&rpmpd MSM8953_VDDCX>,
<&rpmpd MSM8953_VDDMX>,
<&rpmpd MSM8953_VDDMD>;
power-domain-names = "cx", "mx","mss";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "bus", "mem", "xo";
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
resets = <&gcc GCC_MSS_BCR>;
reset-names = "mss_restart";
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
status = "disabled";
mba {
memory-region = <&mba_mem>;
};
mpss {
memory-region = <&mpss_mem>;
};
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
qcom,ipc = <&apcs 8 12>;
qcom,remote-pid = <1>;
label = "modem";
};
};
usb3: usb@70f8800 {
compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
reg = <0x070f8800 0x400>;
@ -1245,6 +1423,72 @@
status = "disabled";
};
wcnss: remoteproc@a21b000 {
compatible = "qcom,pronto-v3-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
memory-region = <&wcnss_fw_mem>;
interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
<&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
power-domains = <&rpmpd MSM8953_VDDCX>,
<&rpmpd MSM8953_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&smp2p_wcnss_out 0>;
qcom,smem-state-names = "stop";
pinctrl-names = "default";
pinctrl-0 = <&wcnss_pin_a>;
status = "disabled";
wcnss_iris: iris {
/* Separate chip, compatible is board-specific */
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
label = "pronto";
wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&wcnss>;
wcnss_bt: bluetooth {
compatible = "qcom,wcnss-bt";
};
wcnss_wifi: wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
qcom,smem-state-names = "tx-enable",
"tx-rings-empty";
};
};
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@ -1315,6 +1559,120 @@
status = "disabled";
};
};
lpass: remoteproc@c200000 {
compatible = "qcom,msm8953-adsp-pil";
reg = <0x0c200000 0x100>;
interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
power-domains = <&rpmpd MSM8953_VDDCX>;
power-domain-names = "cx";
memory-region = <&adsp_fw_mem>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
smd-edge {
interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
mboxes = <&apcs 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
apr {
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
q6core: service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
dai@16 {
reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <0 1>;
};
dai@20 {
reg = <TERTIARY_MI2S_TX>;
qcom,sd-lines = <0 1>;
};
dai@127 {
reg = <QUINARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
};
q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};
q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
dai@0 {
reg = <0>;
direction = <Q6ASM_DAI_RX>;
};
dai@1 {
reg = <1>;
direction = <Q6ASM_DAI_TX>;
};
dai@2 {
reg = <2>;
direction = <Q6ASM_DAI_RX>;
};
dai@3 {
reg = <3>;
direction = <Q6ASM_DAI_RX>;
is-compress-dai;
};
};
};
q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
};
};
};
thermal-zones {

3
arch/arm64/boot/dts/qcom/msm8976.dtsi
View File

@ -1035,7 +1035,8 @@
};
apcs: mailbox@b011000 {
compatible = "qcom,msm8976-apcs-kpss-global", "syscon";
compatible = "qcom,msm8976-apcs-kpss-global",
"qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
};

5
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
View File

@ -60,11 +60,6 @@
reg = <0x0 0x05000000 0x0 0x1a00000>;
no-map;
};
reserved@6c00000 {
reg = <0x0 0x06c00000 0x0 0x400000>;
no-map;
};
};
};

11
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
View File

@ -2,7 +2,7 @@
/*
* Copyright (c) 2015, Huawei Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com>
* Copyright (c) 2021-2023, Petr Vorel <petr.vorel@gmail.com>
*/
/dts-v1/;
@ -31,13 +31,18 @@
#size-cells = <2>;
ranges;
cont_splash_mem: memory@3401000 {
reg = <0 0x03401000 0 0x1000000>;
no-map;
};
tzapp_mem: tzapp@4800000 {
reg = <0 0x04800000 0 0x1900000>;
no-map;
};
removed_region: reserved@6300000 {
reg = <0 0x06300000 0 0xD00000>;
reserved@6300000 {
reg = <0 0x06300000 0 0x700000>;
no-map;
};
};

1
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View File

@ -481,7 +481,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
ts_reset_active: ts-reset-active-state {

6
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -228,6 +228,11 @@
reg = <0 0xc9400000 0 0x3f00000>;
no-map;
};
reserved@6c00000 {
reg = <0 0x06c00000 0 0x400000>;
no-map;
};
};
smd {
@ -840,7 +845,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
i2c5_default: i2c5-default-state {

1
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -1552,7 +1552,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
blsp2_i2c1_default: blsp2-i2c1-state {

1
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
View File

@ -640,7 +640,6 @@
function = "gpio";
bias-disable;
drive-strength = <2>;
input-enable;
};
ts_int_n: ts-int-n-state {

1
arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
View File

@ -501,7 +501,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
ts_int_active: ts-int-active-state {

2
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
View File

@ -844,7 +844,6 @@
function = "gpio";
bias-pull-up;
drive-strength = <2>;
input-enable;
};
chat_cam_pwr_en: chat-cam-pwr-en-default-state {
@ -873,7 +872,6 @@
function = "gpio";
bias-disable;
drive-strength = <2>;
input-enable;
};
ts_int_n: ts-int-n-state {

3
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
View File

@ -528,7 +528,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
mdss_dsi_active_state: mdss-dsi-active-state {
@ -620,7 +619,6 @@
function = "gpio";
drive-strength = <16>;
bias-pull-up;
input-enable;
};
ts_int_suspend_state: ts-int-suspend-state {
@ -642,7 +640,6 @@
function = "gpio";
bias-pull-down;
drive-strength = <2>;
input-enable;
};
wsa_leftspk_pwr_n_state: wsa-leftspk-pwr-n-state {

3
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -2489,7 +2489,8 @@
};
apcs_glb: mailbox@17911000 {
compatible = "qcom,msm8998-apcs-hmss-global";
compatible = "qcom,msm8998-apcs-hmss-global",
"qcom,msm8994-apcs-kpss-global";
reg = <0x17911000 0x1000>;
#mbox-cells = <1>;

63
arch/arm64/boot/dts/qcom/pm2250.dtsi Normal file
View File

@ -0,0 +1,63 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2023, Linaro Ltd
*/
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@0 {
compatible = "qcom,pm2250", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
pm2250_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
debounce = <15625>;
bias-pull-up;
};
pm2250_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm2250_gpios: gpio@c000 {
compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm2250_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmic@1 {
compatible = "qcom,pm2250", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/pm8916.dtsi
View File

@ -41,7 +41,7 @@
};
};
pm8916_usbin: extcon@1300 {
pm8916_usbin: usb-detect@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>;

1561
arch/arm64/boot/dts/qcom/qcm2290.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

1
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View File

@ -296,7 +296,6 @@
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};

3
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -1302,7 +1302,8 @@
};
apcs_glb: mailbox@b011000 {
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
compatible = "qcom,qcs404-apcs-apps-global",
"qcom,msm8916-apcs-kpss-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;

112
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts Normal file
View File

@ -0,0 +1,112 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2023, Linaro Ltd
*/
/dts-v1/;
#include "qcm2290.dtsi"
#include "pm2250.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Robotics RB1";
compatible = "qcom,qrb2210-rb1", "qcom,qrb2210", "qcom,qcm2290";
aliases {
serial0 = &uart0;
sdhc1 = &sdhc_1;
sdhc2 = &sdhc_2;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-0 = <&key_volp_n>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
};
&pm2250_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
non-removable;
supports-cqe;
no-sdio;
no-sd;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdc2_state_on &sd_det_in_on>;
pinctrl-1 = <&sdc2_state_off &sd_det_in_off>;
pinctrl-names = "default", "sleep";
no-sdio;
no-mmc;
status = "okay";
};
&tlmm {
sd_det_in_on: sd-det-in-on-state {
pins = "gpio88";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
sd_det_in_off: sd-det-in-off-state {
pins = "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
key_volp_n: key-volp-n-state {
pins = "gpio96";
function = "gpio";
bias-pull-up;
output-disable;
};
};
/* UART connected to the Micro-USB port via a FTDI chip */
&uart0 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&usb {
status = "okay";
};
&usb_hsphy {
status = "okay";
};
&xo_board {
clock-frequency = <38400000>;
};

227
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts Normal file
View File

@ -0,0 +1,227 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "sm4250.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QRB4210 RB2";
compatible = "qcom,qrb4210-rb2", "qcom,qrb4210", "qcom,sm4250";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&qupv3_id_0 {
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm6125-regulators";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l7-l17-l18-supply = <&vreg_s6a_1p352>;
vdd-l2-l3-l4-supply = <&vreg_s6a_1p352>;
vdd-l5-l15-l19-l20-l21-l22-supply = <&vph_pwr>;
vdd-l6-l8-supply = <&vreg_s5a_0p848>;
vdd-l9-l11-supply = <&vreg_s7a_2p04>;
vdd-l10-l13-l14-supply = <&vreg_s7a_2p04>;
vdd-l12-l16-supply = <&vreg_s7a_2p04>;
vdd-l23-l24-supply = <&vph_pwr>;
vreg_s5a_0p848: s5 {
regulator-min-microvolt = <920000>;
regulator-max-microvolt = <1128000>;
};
vreg_s6a_1p352: s6 {
regulator-min-microvolt = <304000>;
regulator-max-microvolt = <1456000>;
};
vreg_s7a_2p04: s7 {
regulator-min-microvolt = <1280000>;
regulator-max-microvolt = <2080000>;
};
vreg_l1a_1p0: l1 {
regulator-min-microvolt = <952000>;
regulator-max-microvolt = <1152000>;
};
vreg_l4a_0p9: l4 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <1000000>;
};
vreg_l5a_2p96: l5 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <3056000>;
};
vreg_l6a_0p6: l6 {
regulator-min-microvolt = <576000>;
regulator-max-microvolt = <656000>;
};
vreg_l7a_1p256: l7 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
};
vreg_l8a_0p664: l8 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <728000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
};
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1904000>;
};
vreg_l11a_1p8: l11 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1952000>;
};
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1624000>;
regulator-max-microvolt = <1984000>;
};
vreg_l13a_1p8: l13 {
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <1952000>;
};
vreg_l14a_1p8: l14 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1904000>;
};
vreg_l15a_3p128: l15 {
regulator-min-microvolt = <2920000>;
regulator-max-microvolt = <3232000>;
};
vreg_l16a_1p3: l16 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1904000>;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1152000>;
regulator-max-microvolt = <1384000>;
};
vreg_l18a_1p232: l18 {
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1312000>;
};
vreg_l19a_1p8: l19 {
regulator-min-microvolt = <1624000>;
regulator-max-microvolt = <3304000>;
};
vreg_l20a_1p8: l20 {
regulator-min-microvolt = <1624000>;
regulator-max-microvolt = <3304000>;
};
vreg_l21a_2p704: l21 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3600000>;
};
vreg_l22a_2p96: l22 {
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <3304000>;
regulator-system-load = <100000>;
regulator-allow-set-load;
};
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3400000>;
};
vreg_l24a_2p96: l24 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <3600000>;
regulator-system-load = <100000>;
regulator-allow-set-load;
};
};
};
&sdhc_1 {
vmmc-supply = <&vreg_l24a_2p96>;
vqmmc-supply = <&vreg_l11a_1p8>;
no-sdio;
non-removable;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; /* card detect gpio */
vmmc-supply = <&vreg_l22a_2p96>;
vqmmc-supply = <&vreg_l5a_2p96>;
no-sdio;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
gpio-reserved-ranges = <37 5>, <43 2>, <47 1>,
<49 1>, <52 1>, <54 1>,
<56 3>, <61 2>, <64 1>,
<68 1>, <72 8>, <96 1>;
};
&uart4 {
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

233
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sa8775p.dtsi"
#include "sa8775p-pmics.dtsi"
@ -25,6 +27,237 @@
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1816000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1996000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c: ldo3 {
regulator-name = "vreg_l3c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/*
* FIXME: This should have regulator-allow-set-load but
* we're getting an over-current fault from the PMIC
* when switching to LPM.
*/
};
vreg_l5c: ldo5 {
regulator-name = "vreg_l5c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2700000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "e";
vreg_s4e: smps4 {
regulator-name = "vreg_s4e";
regulator-min-microvolt = <970000>;
regulator-max-microvolt = <1520000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s7e: smps7 {
regulator-name = "vreg_s7e";
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9e: smps9 {
regulator-name = "vreg_s9e";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <570000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6e: ldo6 {
regulator-name = "vreg_l6e";
regulator-min-microvolt = <1280000>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8e: ldo8 {
regulator-name = "vreg_l8e";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&i2c18 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c18_default>;

9
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -349,7 +349,7 @@
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
flash@0 {
compatible = "jedec,spi-nor";
@ -507,8 +507,11 @@
bias-disable;
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
&qspi_data0 {
bias-pull-up;
};
&qspi_data1 {
bias-pull-up;
};

41
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -424,8 +424,9 @@
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
pinctrl-1 = <&qspi_sleep>;
flash@0 {
compatible = "jedec,spi-nor";
@ -512,6 +513,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
regulator-boot-on;
};
pp1800_prox:
@ -1044,17 +1047,20 @@ ap_spi_fp: &spi10 {
};
&qspi_cs0 {
bias-disable;
bias-disable; /* External pullup */
};
&qspi_clk {
drive-strength = <8>;
bias-disable;
bias-disable; /* Rely on Cr50 internal pulldown */
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
&qspi_data0 {
bias-disable; /* Rely on Cr50 internal pulldown */
};
&qspi_data1 {
bias-pull-down;
};
&qup_i2c2_default {
@ -1204,7 +1210,6 @@ ap_spi_fp: &spi10 {
ap_ec_int_l: ap-ec-int-l-state {
pins = "gpio94";
function = "gpio";
input-enable;
bias-pull-up;
};
@ -1227,7 +1232,6 @@ ap_spi_fp: &spi10 {
bios_flash_wp_l: bios-flash-wp-l-state {
pins = "gpio66";
function = "gpio";
input-enable;
bias-disable;
};
@ -1269,7 +1273,6 @@ ap_spi_fp: &spi10 {
fp_to_ap_irq_l: fp-to-ap-irq-l-state {
pins = "gpio4";
function = "gpio";
input-enable;
/* Has external pullup */
bias-disable;
@ -1284,7 +1287,6 @@ ap_spi_fp: &spi10 {
h1_ap_int_odl: h1-ap-int-odl-state {
pins = "gpio42";
function = "gpio";
input-enable;
bias-pull-up;
};
@ -1333,12 +1335,27 @@ ap_spi_fp: &spi10 {
p_sensor_int_l: p-sensor-int-l-state {
pins = "gpio24";
function = "gpio";
input-enable;
/* Has external pullup */
bias-disable;
};
qspi_sleep: qspi-sleep-state {
pins = "gpio63", "gpio64", "gpio65", "gpio68";
/*
* When we're not actively transferring we want pins as GPIOs
* with output disabled so that the quad SPI IP block stops
* driving them. We rely on the normal pulls configured in
* the active state and don't redefine them here. Also note
* that we don't need the reverse (output-enable) in the
* normal mode since the "output-enable" only matters for
* GPIO function.
*/
function = "gpio";
output-disable;
};
qup_uart3_sleep: qup-uart3-sleep-state {
cts-pins {
/*

14
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -1543,12 +1543,17 @@
function = "qspi_cs";
};
qspi_data01: qspi-data01-state {
pins = "gpio64", "gpio65";
qspi_data0: qspi-data0-state {
pins = "gpio64";
function = "qspi_data";
};
qspi_data12: qspi-data12-state {
qspi_data1: qspi-data1-state {
pins = "gpio65";
function = "qspi_data";
};
qspi_data23: qspi-data23-state {
pins = "gpio66", "gpio67";
function = "qspi_data";
};
@ -3413,7 +3418,8 @@
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sc7180-apss-shared";
compatible = "qcom,sc7180-apss-shared",
"qcom,sdm845-apss-shared";
reg = <0 0x17c00000 0 0x10000>;
#mbox-cells = <1>;
};

25
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -60,8 +60,9 @@
*/
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
pinctrl-1 = <&qspi_sleep>;
spi_flash: flash@0 {
compatible = "jedec,spi-nor";
@ -85,3 +86,23 @@
iommus = <&apps_smmu 0x1c02 0x1>;
};
};
/* PINCTRL - chrome-common pinctrl */
&tlmm {
qspi_sleep: qspi-sleep-state {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
/*
* When we're not actively transferring we want pins as GPIOs
* with output disabled so that the quad SPI IP block stops
* driving them. We rely on the normal pulls configured in
* the active state and don't redefine them here. Also note
* that we don't need the reverse (output-enable) in the
* normal mode since the "output-enable" only matters for
* GPIO function.
*/
function = "gpio";
output-disable;
};
};

14
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

@ -692,18 +692,22 @@ ap_ec_spi: &spi10 {
};
&qspi_cs0 {
bias-disable;
bias-disable; /* External pullup */
drive-strength = <8>;
};
&qspi_clk {
bias-disable;
bias-pull-down; /* No external pulls */
drive-strength = <8>;
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
&qspi_data0 {
bias-pull-down; /* No external pulls */
drive-strength = <8>;
};
&qspi_data1 {
bias-disable; /* External pulldown */
drive-strength = <8>;
};

2
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
View File

@ -82,14 +82,12 @@ ap_h1_spi: &spi14 {
ap_ec_int_l: ap-ec-int-l-state {
pins = "gpio18";
function = "gpio";
input-enable;
bias-pull-up;
};
h1_ap_int_odl: h1-ap-int-odl-state {
pins = "gpio104";
function = "gpio";
input-enable;
bias-pull-up;
};

13
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -636,16 +636,19 @@
};
&qspi_cs0 {
bias-disable;
bias-disable; /* External pullup */
};
&qspi_clk {
bias-disable;
bias-pull-down; /* No external pulls or external pulldown */
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
&qspi_data0 {
bias-pull-down; /* No external pulls or external pulldown */
};
&qspi_data1 {
bias-pull-down; /* No external pulls or external pulldown */
};
&qup_uart5_tx {

27
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -2140,8 +2140,6 @@
dma-coherent;
iommus = <&apps_smmu 0x1c80 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@ -4355,12 +4353,17 @@
function = "qspi_cs";
};
qspi_data01: qspi-data01-state {
pins = "gpio12", "gpio13";
qspi_data0: qspi-data0-state {
pins = "gpio12";
function = "qspi_data";
};
qspi_data12: qspi-data12-state {
qspi_data1: qspi-data1-state {
pins = "gpio13";
function = "qspi_data";
};
qspi_data23: qspi-data23-state {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
@ -5182,20 +5185,20 @@
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0x17a00000 0 0x10000>, /* GICD */
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic-its@17a40000 {
msi-controller@17a40000 {
compatible = "arm,gic-v3-its";
reg = <0 0x17a40000 0 0x20000>;
msi-controller;
#msi-cells = <1>;
reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};

4
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -870,7 +870,7 @@
pins = "gpio101";
function = "gpio";
bias-disable;
drive-strengh = <16>;
drive-strength = <16>;
output-high;
};
@ -895,7 +895,7 @@
pins = "gpio48";
function = "gpio";
bias-disable;
drive-strengh = <16>;
drive-strength = <16>;
output-high;
};

4
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -1428,7 +1428,7 @@
pins = "gpio101";
function = "gpio";
bias-disable;
drive-strengh = <16>;
drive-strength = <16>;
output-high;
};
@ -1445,7 +1445,7 @@
pins = "gpio48";
function = "gpio";
bias-disable;
drive-strengh = <16>;
drive-strength = <16>;
output-high;
};

12
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -2515,7 +2515,6 @@
status = "disabled";
};
/* RX */
swr1: soundwire-controller@3210000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03210000 0 0x2000>;
@ -2590,13 +2589,13 @@
status = "disabled";
};
/* WSA */
swr0: soundwire-controller@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.6.0";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wsamacro>;
clock-names = "iface";
label = "WSA";
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@ -2618,12 +2617,11 @@
status = "disabled";
};
/* TX */
swr2: soundwire-controller@3330000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03330000 0 0x2000>;
interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
clocks = <&txmacro>;
@ -2728,7 +2726,6 @@
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
@ -2746,7 +2743,6 @@
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
@ -2762,7 +2758,6 @@
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
@ -2780,7 +2775,6 @@
function = "dmic2_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};

41
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -328,6 +328,25 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
dsi_opp_table: opp-table-dsi {
compatible = "operating-points-v2";
opp-131250000 {
opp-hz = /bits/ 64 <131250000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-210000000 {
opp-hz = /bits/ 64 <210000000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-262500000 {
opp-hz = /bits/ 64 <262500000>;
required-opps = <&rpmpd_opp_nom>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
@ -1591,25 +1610,6 @@
status = "disabled";
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-131250000 {
opp-hz = /bits/ 64 <131250000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-210000000 {
opp-hz = /bits/ 64 <210000000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-262500000 {
opp-hz = /bits/ 64 <262500000>;
required-opps = <&rpmpd_opp_nom>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -2267,7 +2267,8 @@
};
apcs_glb: mailbox@17911000 {
compatible = "qcom,sdm660-apcs-hmss-global";
compatible = "qcom,sdm660-apcs-hmss-global",
"qcom,msm8994-apcs-kpss-global";
reg = <0x17911000 0x1000>;
#mbox-cells = <1>;

37
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

@ -317,8 +317,9 @@
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
pinctrl-1 = <&qspi_sleep>;
flash@0 {
compatible = "jedec,spi-nor";
@ -993,16 +994,19 @@ ap_ts_i2c: &i2c14 {
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qspi_cs0 {
bias-disable;
bias-disable; /* External pullup */
};
&qspi_clk {
bias-disable;
bias-disable; /* Rely on Cr50 internal pulldown */
};
&qspi_data01 {
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
&qspi_data0 {
bias-disable; /* Rely on Cr50 internal pulldown */
};
&qspi_data1 {
bias-pull-down;
};
&qup_i2c3_default {
@ -1153,14 +1157,12 @@ ap_ts_i2c: &i2c14 {
bios_flash_wp_r_l: bios-flash-wp-r-l-state {
pins = "gpio128";
function = "gpio";
input-enable;
bias-disable;
};
ec_ap_int_l: ec-ap-int-l-state {
pins = "gpio122";
function = "gpio";
input-enable;
bias-pull-up;
};
@ -1188,7 +1190,6 @@ ap_ts_i2c: &i2c14 {
h1_ap_int_odl: h1-ap-int-odl-state {
pins = "gpio129";
function = "gpio";
input-enable;
bias-pull-up;
};
@ -1234,6 +1235,22 @@ ap_ts_i2c: &i2c14 {
output-high;
};
qspi_sleep: qspi-sleep-state {
pins = "gpio90", "gpio91", "gpio92", "gpio95";
/*
* When we're not actively transferring we want pins as GPIOs
* with output disabled so that the quad SPI IP block stops
* driving them. We rely on the normal pulls configured in
* the active state and don't redefine them here. Also note
* that we don't need the reverse (output-enable) in the
* normal mode since the "output-enable" only matters for
* GPIO function.
*/
function = "gpio";
output-disable;
};
sdc2_clk: sdc2-clk-state {
pins = "sdc2_clk";
bias-disable;

20
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View File

@ -550,6 +550,11 @@
bias-disable;
};
&slpi_pas {
firmware-name = "qcom/sdm845/oneplus6/slpi.mbn";
status = "okay";
};
&sound {
compatible = "qcom,sdm845-sndcard";
pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>;
@ -773,7 +778,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
tri_state_key_default: tri-state-key-default-state {
@ -802,7 +806,6 @@
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
input-enable;
};
panel_esd_pin: panel-esd-state {
@ -810,17 +813,14 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
speaker_default: speaker-default-state {
mux {
pins = "gpio69";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
output-high;
};
pins = "gpio69";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
output-high;
};
};

7
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -572,6 +572,11 @@
status = "okay";
};
&slpi_pas {
firmware-name = "qcom/sdm845/axolotl/slpi.mbn";
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
@ -608,7 +613,6 @@
function = "gpio";
drive-strength = <8>;
bias-pull-up;
input-enable;
};
ts_int_suspend: ts-int-suspend-state {
@ -616,7 +620,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
ts_reset_active: ts-reset-active-state {

1
arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi
View File

@ -80,7 +80,6 @@
pins = "gpio54";
function = "gpio";
input-enable;
bias-pull-down;
drive-strength = <2>;
};

4
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View File

@ -586,7 +586,6 @@
function = "gpio";
bias-pull-down;
drive-strength = <16>;
input-enable;
};
ts_reset_sleep: ts-reset-sleep-state {
@ -601,7 +600,6 @@
function = "gpio";
bias-pull-down;
drive-strength = <2>;
input-enable;
};
sde_dsi_active: sde-dsi-active-state {
@ -712,7 +710,5 @@
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-skip-quirk;
status = "okay";
};

80
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
@ -876,6 +877,14 @@
size = <0 0x4000>;
no-map;
};
fastrpc_mem: fastrpc {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
reusable;
};
};
adsp_pas: remoteproc-adsp {
@ -2329,7 +2338,6 @@
"slave_q2a",
"tbu";
iommus = <&apps_smmu 0x1c10 0xf>;
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
<0x100 &apps_smmu 0x1c11 0x1>,
<0x200 &apps_smmu 0x1c12 0x1>,
@ -2440,7 +2448,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1c00 0xf>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x200 &apps_smmu 0x1c02 0x1>,
@ -2769,12 +2776,17 @@
function = "qspi_cs";
};
qspi_data01: qspi-data01-state {
pins = "gpio91", "gpio92";
qspi_data0: qspi-data0-state {
pins = "gpio91";
function = "qspi_data";
};
qspi_data12: qspi-data12-state {
qspi_data1: qspi-data1-state {
pins = "gpio92";
function = "qspi_data";
};
qspi_data23: qspi-data23-state {
pins = "gpio93", "gpio94";
function = "qspi_data";
};
@ -3174,7 +3186,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
quat_mi2s_active: quat-mi2s-active-state {
@ -3190,7 +3201,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
@ -3205,7 +3215,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
@ -3220,7 +3229,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
@ -3235,7 +3243,6 @@
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
@ -3325,6 +3332,59 @@
"gcc_gpu_gpll0_div_clk_src";
};
slpi_pas: remoteproc@5c00000 {
compatible = "qcom,sdm845-slpi-pas";
reg = <0 0x5c00000 0 0x4000>;
interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
power-domains = <&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
label = "dsps";
qcom,remote-pid = <3>;
mboxes = <&apss_shared 24>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
memory-region = <&fastrpc_mem>;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@0 {
compatible = "qcom,fastrpc-compute-cb";
reg = <0>;
};
};
};
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,

5
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View File

@ -606,7 +606,6 @@
pins = "gpio37";
function = "gpio";
input-enable;
bias-pull-up;
drive-strength = <2>;
};
@ -615,7 +614,6 @@
pins = "gpio125";
function = "gpio";
input-enable;
bias-pull-up;
drive-strength = <2>;
};
@ -624,7 +622,6 @@
pins = "gpio92";
function = "gpio";
input-enable;
bias-pull-up;
drive-strength = <2>;
};
@ -633,7 +630,6 @@
pins = "gpio124";
function = "gpio";
input-enable;
bias-disable;
};
@ -641,7 +637,6 @@
pins = "gpio95";
function = "gpio";
input-enable;
bias-disable;
};
};

15
arch/arm64/boot/dts/qcom/sm6115.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@ -290,6 +291,15 @@
reg = <0x0 0x60000000 0x0 0x3900000>;
no-map;
};
rmtfs_mem: memory@89b01000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x89b01000 0x0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
};
};
rpm-glink {
@ -1241,7 +1251,7 @@
};
mdss_dsi0: dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290";
compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x05e94000 0x0 0x400>;
reg-names = "dsi_ctrl";
@ -2244,7 +2254,8 @@
};
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6115-apcs-hmss-global";
compatible = "qcom,sm6115-apcs-hmss-global",
"qcom,msm8994-apcs-kpss-global";
reg = <0x0 0x0f111000 0x0 0x1000>;
#mbox-cells = <1>;

35
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts
View File

@ -52,6 +52,17 @@
wakeup-source;
};
};
reserved-memory {
ramoops@ffc00000 {
compatible = "ramoops";
reg = <0x0 0xffc00000 0x0 0x100000>;
record-size = <0x1000>;
console-size = <0x40000>;
ftrace-size = <0x20000>;
ecc-size = <16>;
};
};
};
&dispcc {
@ -78,6 +89,21 @@
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/sm6115/LENOVO/J606F/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/sm6115/LENOVO/J606F/cdsp.mbn";
status = "okay";
};
&remoteproc_mpss {
firmware-name = "qcom/sm6115/LENOVO/J606F/modem.mbn";
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm6125-regulators";
@ -289,6 +315,15 @@
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&pm6125_l8>;
vdd-1.8-xo-supply = <&pm6125_l16>;
vdd-1.3-rfa-supply = <&pm6125_l17>;
vdd-3.3-ch0-supply = <&pm6125_l23>;
qcom,ath10k-calibration-variant = "Lenovo_P11";
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

1
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
View File

@ -468,7 +468,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
};

421
arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts Normal file
View File

@ -0,0 +1,421 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Lux Aliaga <they@mint.lgbt>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sm6125.dtsi"
#include "pm6125.dtsi"
/ {
model = "Xiaomi Mi A3";
compatible = "xiaomi,laurel-sprout", "qcom,sm6125";
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <394 0>; /* sm6125 v1 */
qcom,board-id = <11 0>;
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer0: framebuffer@5c000000 {
compatible = "simple-framebuffer";
reg = <0 0x5c000000 0 (1560 * 720 * 4)>;
width = <720>;
height = <1560>;
stride = <(720 * 4)>;
format = "a8r8g8b8";
};
};
reserved-memory {
debug_mem: debug@ffb00000 {
reg = <0x0 0xffb00000 0x0 0xc0000>;
no-map;
};
last_log_mem: lastlog@ffbc0000 {
reg = <0x0 0xffbc0000 0x0 0x80000>;
no-map;
};
pstore_mem: ramoops@ffc00000 {
compatible = "ramoops";
reg = <0x0 0xffc40000 0x0 0xc0000>;
record-size = <0x1000>;
console-size = <0x40000>;
msg-size = <0x20000 0x20000>;
};
cmdline_mem: memory@ffd00000 {
reg = <0x0 0xffd40000 0x0 0x1000>;
no-map;
};
};
extcon_usb: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&vol_up_n>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
thermal-zones {
rf-pa0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
quiet-thermal {
polling-delay-passive = <0>;
polling-delay = <5000>;
thermal-sensors = <&pm6125_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
xo-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
};
&hsusb_phy1 {
vdd-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l10a>;
vdda-phy-dpdm-supply = <&vreg_l15a>;
status = "okay";
};
&pm6125_adc {
pinctrl-names = "default";
pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>;
adc-chan@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "rf_pa0_therm";
};
adc-chan@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "quiet_therm";
};
adc-chan@52 {
reg = <ADC5_GPIO1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "camera_flash_therm";
};
adc-chan@54 {
reg = <ADC5_GPIO3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "emmc_ufs_therm";
};
};
&pm6125_adc_tm {
status = "okay";
rf-pa0-therm@0 {
reg = <0>;
io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
quiet-therm@1 {
reg = <1>;
io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
xo-therm@2 {
reg = <2>;
io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm6125_gpios {
camera_flash_therm: camera-flash-therm-state {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
bias-high-impedance;
};
emmc_ufs_therm: emmc-ufs-therm-state {
pins = "gpio6";
function = PMIC_GPIO_FUNC_NORMAL;
bias-high-impedance;
};
vol_up_n: vol-up-n-state {
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-up;
};
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm6125-regulators";
vreg_s6a: s6 {
regulator-min-microvolt = <936000>;
regulator-max-microvolt = <1422000>;
};
vreg_l1a: l1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1256000>;
};
vreg_l2a: l2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1056000>;
};
vreg_l3a: l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1064000>;
};
vreg_l4a: l4 {
regulator-min-microvolt = <872000>;
regulator-max-microvolt = <976000>;
regulator-allow-set-load;
};
vreg_l5a: l5 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
vreg_l6a: l6 {
regulator-min-microvolt = <576000>;
regulator-max-microvolt = <656000>;
};
vreg_l7a: l7 {
regulator-min-microvolt = <872000>;
regulator-max-microvolt = <976000>;
};
vreg_l8a: l8 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <728000>;
};
vreg_l9a: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1896000>;
};
vreg_l10a: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1896000>;
regulator-allow-set-load;
};
vreg_l11a: l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1952000>;
regulator-allow-set-load;
};
vreg_l12a: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1996000>;
};
vreg_l13a: l13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1832000>;
};
vreg_l14a: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1904000>;
};
vreg_l15a: l15 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3232000>;
};
vreg_l16a: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1904000>;
};
vreg_l17a: l17 {
regulator-min-microvolt = <1248000>;
regulator-max-microvolt = <1304000>;
};
vreg_l18a: l18 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1264000>;
regulator-allow-set-load;
};
vreg_l19a: l19 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <2952000>;
};
vreg_l20a: l20 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <2952000>;
};
vreg_l21a: l21 {
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2856000>;
};
vreg_l22a: l22 {
regulator-min-microvolt = <2944000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
vreg_l23a: l23 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3400000>;
};
vreg_l24a: l24 {
regulator-min-microvolt = <2944000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
};
};
&sdc2_off_state {
sd-cd-pins {
pins = "gpio98";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
&sdc2_on_state {
sd-cd-pins {
pins = "gpio98";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
&sdhc_2 {
cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vreg_l22a>;
vqmmc-supply = <&vreg_l5a>;
no-sdio;
no-mmc;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <22 2>, <28 6>;
};
&ufs_mem_hc {
vcc-supply = <&vreg_l24a>;
vccq2-supply = <&vreg_l11a>;
vcc-max-microamp = <600000>;
vccq2-max-microamp = <600000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l10a>;
vdda-phy-max-microamp = <51400>;
vdda-pll-max-microamp = <14200>;
vddp-ref-clk-supply = <&vreg_l18a>;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
extcon = <&extcon_usb>;
};

67
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@ -737,6 +737,70 @@
status = "disabled";
};
ufs_mem_hc: ufs@4804000 {
compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"ice_core_clk";
freq-table-hz = <50000000 240000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<0 0>,
<0 0>,
<0 0>,
<75000000 300000000>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
#reset-cells = <1>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
iommus = <&apps_smmu 0x200 0x0>;
status = "disabled";
};
ufs_mem_phy: phy@4807000 {
compatible = "qcom,sm6125-qmp-ufs-phy";
reg = <0x04807000 0xdb8>;
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref",
"ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
power-domains = <&gcc UFS_PHY_GDSC>;
#phy-cells = <0>;
status = "disabled";
};
gpi_dma0: dma-controller@4a00000 {
compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x04a00000 0x60000>;
@ -1210,7 +1274,8 @@
};
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6125-apcs-hmss-global";
compatible = "qcom,sm6125-apcs-hmss-global",
"qcom,msm8994-apcs-kpss-global";
reg = <0x0f111000 0x1000>;
#mbox-cells = <1>;

1
arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
View File

@ -367,7 +367,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
};

5
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
View File

@ -359,6 +359,11 @@
};
&gpu {
/*
* NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
* after display support is added on this board.
*/
compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
status = "okay";
};

1
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View File

@ -479,7 +479,6 @@
pins = "gpio42";
function = "gpio";
bias-pull-up;
input-enable;
};
};

5
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
View File

@ -354,6 +354,11 @@
};
&gpu {
/*
* NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
* after display support is added on this board.
*/
compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
status = "okay";
};

36
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -950,6 +950,17 @@
status = "disabled";
};
qfprom: efuse@784000 {
compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
@ -1848,7 +1859,6 @@
"slave_q2a",
"tbu";
iommus = <&apps_smmu 0x1d80 0x3f>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@ -1947,7 +1957,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1e00 0x3f>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
@ -2155,15 +2164,7 @@
};
gpu: gpu@2c00000 {
/*
* note: the amd,imageon compatible makes it possible
* to use the drm/msm driver without the display node,
* make sure to remove it when display node is added
*/
compatible = "qcom,adreno-640.1",
"qcom,adreno",
"amd,imageon";
compatible = "qcom,adreno-640.1", "qcom,adreno";
reg = <0 0x02c00000 0 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
@ -2175,44 +2176,52 @@
qcom,gmu = <&gmu>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
status = "disabled";
zap-shader {
memory-region = <&gpu_mem>;
};
/* note: downstream checks gpu binning for 675 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-supported-hw = <0x2>;
};
opp-585000000 {
opp-hz = /bits/ 64 <585000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-supported-hw = <0x3>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-supported-hw = <0x3>;
};
opp-427000000 {
opp-hz = /bits/ 64 <427000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-supported-hw = <0x3>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-supported-hw = <0x3>;
};
opp-257000000 {
opp-hz = /bits/ 64 <257000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-supported-hw = <0x3>;
};
};
};
@ -4126,7 +4135,8 @@
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sm8150-apss-shared";
compatible = "qcom,sm8150-apss-shared",
"qcom,sdm845-apss-shared";
reg = <0x0 0x17c00000 0x0 0x1000>;
#mbox-cells = <1>;
};

1
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
View File

@ -625,7 +625,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
ap2mdm_default: ap2mdm-default-state {

18
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Jianhua Lu <lujianhua000@gmail.com>
*/
/dts-v1/;
#include "sm8250-xiaomi-elish-common.dtsi"
/ {
model = "Xiaomi Mi Pad 5 Pro (BOE)";
compatible = "xiaomi,elish", "qcom,sm8250";
};
&display_panel {
compatible = "xiaomi,elish-boe-nt36523";
status = "okay";
};

79
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts → arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
View File

@ -3,9 +3,8 @@
* Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
@ -24,8 +23,6 @@
/delete-node/ &xbl_aop_mem;
/ {
model = "Xiaomi Mi Pad 5 Pro";
compatible = "xiaomi,elish", "qcom,sm8250";
classis-type = "tablet";
/* required for bootloader to select correct board */
@ -473,6 +470,76 @@
status = "okay";
};
&dsi0 {
vdda-supply = <&vreg_l9a_1p2>;
qcom,dual-dsi-mode;
qcom,sync-dual-dsi;
qcom,master-dsi;
status = "okay";
display_panel: panel@0 {
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
backlight = <&backlight>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1{
reg = <1>;
panel_in_1: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};
};
&dsi0_out {
data-lanes = <0 1 2>;
remote-endpoint = <&panel_in_0>;
};
&dsi0_phy {
vdds-supply = <&vreg_l5a_0p88>;
phy-type = <PHY_TYPE_CPHY>;
status = "okay";
};
&dsi1 {
vdda-supply = <&vreg_l9a_1p2>;
qcom,dual-dsi-mode;
qcom,sync-dual-dsi;
/* DSI1 is slave, so use DSI0 clocks */
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
status = "okay";
};
&dsi1_out {
data-lanes = <0 1 2>;
remote-endpoint = <&panel_in_1>;
};
&dsi1_phy {
vdds-supply = <&vreg_l5a_0p88>;
phy-type = <PHY_TYPE_CPHY>;
status = "okay";
};
&gmu {
status = "okay";
};
@ -537,6 +604,10 @@
};
};
&mdss {
status = "okay";
};
&pcie0 {
status = "okay";
};

18
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Jianhua Lu <lujianhua000@gmail.com>
*/
/dts-v1/;
#include "sm8250-xiaomi-elish-common.dtsi"
/ {
model = "Xiaomi Mi Pad 5 Pro (CSOT)";
compatible = "xiaomi,elish", "qcom,sm8250";
};
&display_panel {
compatible = "xiaomi,elish-csot-nt36523";
status = "okay";
};

35
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -960,6 +960,18 @@
#mbox-cells = <2>;
};
qfprom: efuse@784000 {
compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@19b {
reg = <0x19b 0x1>;
bits = <5 3>;
};
};
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
@ -1877,7 +1889,6 @@
"tbu",
"ddrss_sf_tbu";
iommus = <&apps_smmu 0x1c00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
@ -1984,7 +1995,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@ -2093,7 +2103,6 @@
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1d00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
@ -2367,7 +2376,7 @@
swr2: soundwire-controller@3230000 {
reg = <0 0x03230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core";
status = "disabled";
@ -2436,7 +2445,6 @@
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
@ -2444,7 +2452,6 @@
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
};
@ -2460,7 +2467,6 @@
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
@ -2478,7 +2484,6 @@
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
@ -2523,7 +2528,6 @@
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
@ -2531,7 +2535,6 @@
pins = "gpio1";
function = "swr_tx_data";
drive-strength = <2>;
input-enable;
bias-bus-hold;
};
@ -2539,7 +2542,6 @@
pins = "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
input-enable;
bias-pull-down;
};
};
@ -2560,49 +2562,58 @@
qcom,gmu = <&gmu>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
status = "disabled";
zap-shader {
memory-region = <&gpu_mem>;
};
/* note: downstream checks gpu binning for 670 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-670000000 {
opp-hz = /bits/ 64 <670000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-supported-hw = <0xa>;
};
opp-587000000 {
opp-hz = /bits/ 64 <587000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-supported-hw = <0xb>;
};
opp-525000000 {
opp-hz = /bits/ 64 <525000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-supported-hw = <0xf>;
};
opp-490000000 {
opp-hz = /bits/ 64 <490000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-supported-hw = <0xf>;
};
opp-441600000 {
opp-hz = /bits/ 64 <441600000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
opp-supported-hw = <0xf>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-supported-hw = <0xf>;
};
opp-305000000 {
opp-hz = /bits/ 64 <305000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-supported-hw = <0xf>;
};
};
};

1
arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
View File

@ -877,7 +877,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
sdc2_card_det_active: sd-card-det-active-state {

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1532,7 +1532,6 @@
"aggre1",
"aggre0";
iommus = <&apps_smmu 0x1c00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
@ -1616,7 +1615,6 @@
"ddrss_sf_tbu",
"aggre1";
iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;

1
arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
View File

@ -754,7 +754,6 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
telec_pwr_en: telec-pwr-en-state {

12
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -1786,7 +1786,6 @@
"aggre0",
"aggre1";
iommus = <&apps_smmu 0x1c00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
@ -1899,7 +1898,6 @@
"ddrss_sf_tbu",
"aggre1";
iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@ -2135,13 +2133,13 @@
#sound-dai-cells = <1>;
};
/* WSA2 */
swr4: soundwire-controller@31f0000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x031f0000 0 0x2000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wsa2macro>;
clock-names = "iface";
label = "WSA2";
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@ -2250,13 +2248,13 @@
#sound-dai-cells = <1>;
};
/* WSA */
swr0: soundwire-controller@3250000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x03250000 0 0x2000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wsamacro>;
clock-names = "iface";
label = "WSA";
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@ -2280,8 +2278,8 @@
swr2: soundwire-controller@33b0000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x033b0000 0 0x2000>;
interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
clocks = <&vamacro>;
@ -3690,7 +3688,6 @@
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
@ -3706,7 +3703,6 @@
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};

315
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -1698,7 +1698,6 @@
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommus = <&apps_smmu 0x1400 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
@ -1795,7 +1794,6 @@
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommus = <&apps_smmu 0x1480 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>;
@ -1927,9 +1925,18 @@
<0 0>,
<0 0>,
<0 0>;
qcom,ice = <&ice>;
status = "disabled";
};
ice: crypto@1d88000 {
compatible = "qcom,sm8550-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0 0x01d88000 0 0x8000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
@ -1986,6 +1993,206 @@
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
pinctrl-names = "default";
pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
swr3: soundwire-controller@6ab0000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06ab0000 0 0x10000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsa2macro>;
clock-names = "iface";
label = "WSA2";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_rxmacro: codec@6ac0000 {
compatible = "qcom,sm8550-lpass-rx-macro";
reg = <0 0x06ac0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
swr1: soundwire-controller@6ad0000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06ad0000 0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_rxmacro>;
clock-names = "iface";
label = "RX";
qcom,din-ports = <0>;
qcom,dout-ports = <10>;
qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_txmacro: codec@6ae0000 {
compatible = "qcom,sm8550-lpass-tx-macro";
reg = <0 0x06ae0000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
lpass_wsamacro: codec@6b00000 {
compatible = "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06b00000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
swr0: soundwire-controller@6b10000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06b10000 0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsamacro>;
clock-names = "iface";
label = "WSA";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
swr2: soundwire-controller@6d30000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06d30000 0 0x10000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
clocks = <&lpass_vamacro>;
clock-names = "iface";
label = "TX";
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_vamacro: codec@6d44000 {
compatible = "qcom,sm8550-lpass-va-macro";
reg = <0 0x06d44000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec";
assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
lpass_tlmm: pinctrl@6e80000 {
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
reg = <0 0x06e80000 0 0x20000>,
@ -1997,6 +2204,110 @@
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
tx_swr_active: tx-swr-active-state {
clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
dmic02_default: dmic02-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
wsa2_swr_active: wsa2-swr-active-state {
clk-pins {
pins = "gpio15";
function = "wsa2_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio16";
function = "wsa2_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
};
lpass_lpiaon_noc: interconnect@7400000 {

36
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -323,6 +323,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
break;
case PIN_CONFIG_OUTPUT:
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
*bit = g->oe_bit;
*mask = 1;
break;
@ -414,11 +415,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
val = msm_readl_io(pctrl, g);
arg = !!(val & BIT(g->in_bit));
break;
case PIN_CONFIG_INPUT_ENABLE:
/* Pin is output */
if (arg)
case PIN_CONFIG_OUTPUT_ENABLE:
if (!arg)
return -EINVAL;
arg = 1;
break;
default:
return -ENOTSUPP;
@ -502,9 +501,36 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
arg = 1;
break;
case PIN_CONFIG_INPUT_ENABLE:
/* disable output */
/*
* According to pinctrl documentation this should
* actually be a no-op.
*
* The docs are explicit that "this does not affect
* the pin's ability to drive output" but what we do
* here is to modify the output enable bit. Thus, to
* follow the docs we should remove that.
*
* The docs say that we should enable any relevant
* input buffer, but TLMM there is no input buffer that
* can be enabled/disabled. It's always on.
*
* The points above, explain why this _should_ be a
* no-op. However, for historical reasons and to
* support old device trees, we'll violate the docs
* still affect the output.
*
* It should further be noted that this old historical
* behavior actually overrides arg to 0. That means
* that "input-enable" and "input-disable" in a device
* tree would _both_ disable the output. We'll
* continue to preserve this behavior as well since
* we have no other use for this attribute.
*/
arg = 0;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
arg = !!arg;
break;
default:
dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
param);

213
include/dt-bindings/clock/qcom,ipq9574-gcc.h Normal file
View File

@ -0,0 +1,213 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2023 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
#define GPLL0_MAIN 0
#define GPLL0 1
#define GPLL2_MAIN 2
#define GPLL2 3
#define GPLL4_MAIN 4
#define GPLL4 5
#define GCC_SLEEP_CLK_SRC 6
#define APSS_AHB_CLK_SRC 7
#define APSS_AXI_CLK_SRC 8
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 15
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 16
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 17
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 18
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 19
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 20
#define BLSP1_UART1_APPS_CLK_SRC 21
#define BLSP1_UART2_APPS_CLK_SRC 22
#define BLSP1_UART3_APPS_CLK_SRC 23
#define BLSP1_UART4_APPS_CLK_SRC 24
#define BLSP1_UART5_APPS_CLK_SRC 25
#define BLSP1_UART6_APPS_CLK_SRC 26
#define GCC_APSS_AHB_CLK 27
#define GCC_APSS_AXI_CLK 28
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 37
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 38
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 39
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 40
#define GCC_BLSP1_UART1_APPS_CLK 41
#define GCC_BLSP1_UART2_APPS_CLK 42
#define GCC_BLSP1_UART3_APPS_CLK 43
#define GCC_BLSP1_UART4_APPS_CLK 44
#define GCC_BLSP1_UART5_APPS_CLK 45
#define GCC_BLSP1_UART6_APPS_CLK 46
#define PCIE0_AXI_M_CLK_SRC 47
#define GCC_PCIE0_AXI_M_CLK 48
#define PCIE1_AXI_M_CLK_SRC 49
#define GCC_PCIE1_AXI_M_CLK 50
#define PCIE2_AXI_M_CLK_SRC 51
#define GCC_PCIE2_AXI_M_CLK 52
#define PCIE3_AXI_M_CLK_SRC 53
#define GCC_PCIE3_AXI_M_CLK 54
#define PCIE0_AXI_S_CLK_SRC 55
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 56
#define GCC_PCIE0_AXI_S_CLK 57
#define PCIE1_AXI_S_CLK_SRC 58
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 59
#define GCC_PCIE1_AXI_S_CLK 60
#define PCIE2_AXI_S_CLK_SRC 61
#define GCC_PCIE2_AXI_S_BRIDGE_CLK 62
#define GCC_PCIE2_AXI_S_CLK 63
#define PCIE3_AXI_S_CLK_SRC 64
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
#define GCC_PCIE3_AXI_S_CLK 66
#define PCIE0_PIPE_CLK_SRC 67
#define PCIE1_PIPE_CLK_SRC 68
#define PCIE2_PIPE_CLK_SRC 69
#define PCIE3_PIPE_CLK_SRC 70
#define PCIE_AUX_CLK_SRC 71
#define GCC_PCIE0_AUX_CLK 72
#define GCC_PCIE1_AUX_CLK 73
#define GCC_PCIE2_AUX_CLK 74
#define GCC_PCIE3_AUX_CLK 75
#define PCIE0_RCHNG_CLK_SRC 76
#define GCC_PCIE0_RCHNG_CLK 77
#define PCIE1_RCHNG_CLK_SRC 78
#define GCC_PCIE1_RCHNG_CLK 79
#define PCIE2_RCHNG_CLK_SRC 80
#define GCC_PCIE2_RCHNG_CLK 81
#define PCIE3_RCHNG_CLK_SRC 82
#define GCC_PCIE3_RCHNG_CLK 83
#define GCC_PCIE0_AHB_CLK 84
#define GCC_PCIE1_AHB_CLK 85
#define GCC_PCIE2_AHB_CLK 86
#define GCC_PCIE3_AHB_CLK 87
#define USB0_AUX_CLK_SRC 88
#define GCC_USB0_AUX_CLK 89
#define USB0_MASTER_CLK_SRC 90
#define GCC_USB0_MASTER_CLK 91
#define GCC_SNOC_USB_CLK 92
#define GCC_ANOC_USB_AXI_CLK 93
#define USB0_MOCK_UTMI_CLK_SRC 94
#define USB0_MOCK_UTMI_DIV_CLK_SRC 95
#define GCC_USB0_MOCK_UTMI_CLK 96
#define USB0_PIPE_CLK_SRC 97
#define GCC_USB0_PHY_CFG_AHB_CLK 98
#define SDCC1_APPS_CLK_SRC 99
#define GCC_SDCC1_APPS_CLK 100
#define SDCC1_ICE_CORE_CLK_SRC 101
#define GCC_SDCC1_ICE_CORE_CLK 102
#define GCC_SDCC1_AHB_CLK 103
#define PCNOC_BFDCD_CLK_SRC 104
#define GCC_NSSCFG_CLK 105
#define GCC_NSSNOC_NSSCC_CLK 106
#define GCC_NSSCC_CLK 107
#define GCC_NSSNOC_PCNOC_1_CLK 108
#define GCC_QDSS_DAP_AHB_CLK 109
#define GCC_QDSS_CFG_AHB_CLK 110
#define GCC_QPIC_AHB_CLK 111
#define GCC_QPIC_CLK 112
#define GCC_BLSP1_AHB_CLK 113
#define GCC_MDIO_AHB_CLK 114
#define GCC_PRNG_AHB_CLK 115
#define GCC_UNIPHY0_AHB_CLK 116
#define GCC_UNIPHY1_AHB_CLK 117
#define GCC_UNIPHY2_AHB_CLK 118
#define GCC_CMN_12GPLL_AHB_CLK 119
#define GCC_CMN_12GPLL_APU_CLK 120
#define SYSTEM_NOC_BFDCD_CLK_SRC 121
#define GCC_NSSNOC_SNOC_CLK 122
#define GCC_NSSNOC_SNOC_1_CLK 123
#define GCC_QDSS_ETR_USB_CLK 124
#define WCSS_AHB_CLK_SRC 125
#define GCC_Q6_AHB_CLK 126
#define GCC_Q6_AHB_S_CLK 127
#define GCC_WCSS_ECAHB_CLK 128
#define GCC_WCSS_ACMT_CLK 129
#define GCC_SYS_NOC_WCSS_AHB_CLK 130
#define WCSS_AXI_M_CLK_SRC 131
#define GCC_ANOC_WCSS_AXI_M_CLK 132
#define QDSS_AT_CLK_SRC 133
#define GCC_Q6SS_ATBM_CLK 134
#define GCC_WCSS_DBG_IFC_ATB_CLK 135
#define GCC_NSSNOC_ATB_CLK 136
#define GCC_QDSS_AT_CLK 137
#define GCC_SYS_NOC_AT_CLK 138
#define GCC_PCNOC_AT_CLK 139
#define GCC_USB0_EUD_AT_CLK 140
#define GCC_QDSS_EUD_AT_CLK 141
#define QDSS_STM_CLK_SRC 142
#define GCC_QDSS_STM_CLK 143
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144
#define QDSS_TRACECLKIN_CLK_SRC 145
#define GCC_QDSS_TRACECLKIN_CLK 146
#define QDSS_TSCTR_CLK_SRC 147
#define GCC_Q6_TSCTR_1TO2_CLK 148
#define GCC_WCSS_DBG_IFC_NTS_CLK 149
#define GCC_QDSS_TSCTR_DIV2_CLK 150
#define GCC_QDSS_TS_CLK 151
#define GCC_QDSS_TSCTR_DIV4_CLK 152
#define GCC_NSS_TS_CLK 153
#define GCC_QDSS_TSCTR_DIV8_CLK 154
#define GCC_QDSS_TSCTR_DIV16_CLK 155
#define GCC_Q6SS_PCLKDBG_CLK 156
#define GCC_Q6SS_TRIG_CLK 157
#define GCC_WCSS_DBG_IFC_APB_CLK 158
#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159
#define GCC_QDSS_DAP_CLK 160
#define GCC_QDSS_APB2JTAG_CLK 161
#define GCC_QDSS_TSCTR_DIV3_CLK 162
#define QPIC_IO_MACRO_CLK_SRC 163
#define GCC_QPIC_IO_MACRO_CLK 164
#define Q6_AXI_CLK_SRC 165
#define GCC_Q6_AXIM_CLK 166
#define GCC_WCSS_Q6_TBU_CLK 167
#define GCC_MEM_NOC_Q6_AXI_CLK 168
#define Q6_AXIM2_CLK_SRC 169
#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170
#define GCC_NSSNOC_MEMNOC_CLK 171
#define GCC_NSSNOC_MEM_NOC_1_CLK 172
#define GCC_NSS_TBU_CLK 173
#define GCC_MEM_NOC_NSSNOC_CLK 174
#define LPASS_AXIM_CLK_SRC 175
#define LPASS_SWAY_CLK_SRC 176
#define ADSS_PWM_CLK_SRC 177
#define GCC_ADSS_PWM_CLK 178
#define GP1_CLK_SRC 179
#define GP2_CLK_SRC 180
#define GP3_CLK_SRC 181
#define DDRSS_SMS_SLOW_CLK_SRC 182
#define GCC_XO_CLK_SRC 183
#define GCC_XO_CLK 184
#define GCC_NSSNOC_QOSGEN_REF_CLK 185
#define GCC_NSSNOC_TIMEOUT_REF_CLK 186
#define GCC_XO_DIV4_CLK 187
#define GCC_UNIPHY0_SYS_CLK 188
#define GCC_UNIPHY1_SYS_CLK 189
#define GCC_UNIPHY2_SYS_CLK 190
#define GCC_CMN_12GPLL_SYS_CLK 191
#define GCC_NSSNOC_XO_DCD_CLK 192
#define GCC_Q6SS_BOOT_CLK 193
#define UNIPHY_SYS_CLK_SRC 194
#define NSS_TS_CLK_SRC 195
#define GCC_ANOC_PCIE0_1LANE_M_CLK 196
#define GCC_ANOC_PCIE1_1LANE_M_CLK 197
#define GCC_ANOC_PCIE2_2LANE_M_CLK 198
#define GCC_ANOC_PCIE3_2LANE_M_CLK 199
#define GCC_SNOC_PCIE0_1LANE_S_CLK 200
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
#endif

2
include/dt-bindings/firmware/qcom,scm.h
View File

@ -8,6 +8,8 @@
#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
#define QCOM_SCM_VMID_HLOS 0x3
#define QCOM_SCM_VMID_SSC_Q6 0x5
#define QCOM_SCM_VMID_ADSP_Q6 0x6
#define QCOM_SCM_VMID_MSS_MSA 0xF
#define QCOM_SCM_VMID_WLAN 0x18
#define QCOM_SCM_VMID_WLAN_CE 0x19

164
include/dt-bindings/reset/qcom,ipq9574-gcc.h Normal file
View File

@ -0,0 +1,164 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H
#define GCC_ADSS_BCR 0
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1
#define GCC_BLSP1_BCR 2
#define GCC_BLSP1_QUP1_BCR 3
#define GCC_BLSP1_QUP2_BCR 4
#define GCC_BLSP1_QUP3_BCR 5
#define GCC_BLSP1_QUP4_BCR 6
#define GCC_BLSP1_QUP5_BCR 7
#define GCC_BLSP1_QUP6_BCR 8
#define GCC_BLSP1_UART1_BCR 9
#define GCC_BLSP1_UART2_BCR 10
#define GCC_BLSP1_UART3_BCR 11
#define GCC_BLSP1_UART4_BCR 12
#define GCC_BLSP1_UART5_BCR 13
#define GCC_BLSP1_UART6_BCR 14
#define GCC_BOOT_ROM_BCR 15
#define GCC_MDIO_BCR 16
#define GCC_NSS_BCR 17
#define GCC_NSS_TBU_BCR 18
#define GCC_PCIE0_BCR 19
#define GCC_PCIE0_LINK_DOWN_BCR 20
#define GCC_PCIE0_PHY_BCR 21
#define GCC_PCIE0PHY_PHY_BCR 22
#define GCC_PCIE1_BCR 23
#define GCC_PCIE1_LINK_DOWN_BCR 24
#define GCC_PCIE1_PHY_BCR 25
#define GCC_PCIE1PHY_PHY_BCR 26
#define GCC_PCIE2_BCR 27
#define GCC_PCIE2_LINK_DOWN_BCR 28
#define GCC_PCIE2_PHY_BCR 29
#define GCC_PCIE2PHY_PHY_BCR 30
#define GCC_PCIE3_BCR 31
#define GCC_PCIE3_LINK_DOWN_BCR 32
#define GCC_PCIE3_PHY_BCR 33
#define GCC_PCIE3PHY_PHY_BCR 34
#define GCC_PRNG_BCR 35
#define GCC_QUSB2_0_PHY_BCR 36
#define GCC_SDCC_BCR 37
#define GCC_TLMM_BCR 38
#define GCC_UNIPHY0_BCR 39
#define GCC_UNIPHY1_BCR 40
#define GCC_UNIPHY2_BCR 41
#define GCC_USB0_PHY_BCR 42
#define GCC_USB3PHY_0_PHY_BCR 43
#define GCC_USB_BCR 44
#define GCC_ANOC0_TBU_BCR 45
#define GCC_ANOC1_TBU_BCR 46
#define GCC_ANOC_BCR 47
#define GCC_APSS_TCU_BCR 48
#define GCC_CMN_BLK_BCR 49
#define GCC_CMN_BLK_AHB_ARES 50
#define GCC_CMN_BLK_SYS_ARES 51
#define GCC_CMN_BLK_APU_ARES 52
#define GCC_DCC_BCR 53
#define GCC_DDRSS_BCR 54
#define GCC_IMEM_BCR 55
#define GCC_LPASS_BCR 56
#define GCC_MPM_BCR 57
#define GCC_MSG_RAM_BCR 58
#define GCC_NSSNOC_MEMNOC_1_ARES 59
#define GCC_NSSNOC_PCNOC_1_ARES 60
#define GCC_NSSNOC_SNOC_1_ARES 61
#define GCC_NSSNOC_XO_DCD_ARES 62
#define GCC_NSSNOC_TS_ARES 63
#define GCC_NSSCC_ARES 64
#define GCC_NSSNOC_NSSCC_ARES 65
#define GCC_NSSNOC_ATB_ARES 66
#define GCC_NSSNOC_MEMNOC_ARES 67
#define GCC_NSSNOC_QOSGEN_REF_ARES 68
#define GCC_NSSNOC_SNOC_ARES 69
#define GCC_NSSNOC_TIMEOUT_REF_ARES 70
#define GCC_NSS_CFG_ARES 71
#define GCC_UBI0_DBG_ARES 72
#define GCC_PCIE0_AHB_ARES 73
#define GCC_PCIE0_AUX_ARES 74
#define GCC_PCIE0_AXI_M_ARES 75
#define GCC_PCIE0_AXI_M_STICKY_ARES 76
#define GCC_PCIE0_AXI_S_ARES 77
#define GCC_PCIE0_AXI_S_STICKY_ARES 78
#define GCC_PCIE0_CORE_STICKY_ARES 79
#define GCC_PCIE0_PIPE_ARES 80
#define GCC_PCIE1_AHB_ARES 81
#define GCC_PCIE1_AUX_ARES 82
#define GCC_PCIE1_AXI_M_ARES 83
#define GCC_PCIE1_AXI_M_STICKY_ARES 84
#define GCC_PCIE1_AXI_S_ARES 85
#define GCC_PCIE1_AXI_S_STICKY_ARES 86
#define GCC_PCIE1_CORE_STICKY_ARES 87
#define GCC_PCIE1_PIPE_ARES 88
#define GCC_PCIE2_AHB_ARES 89
#define GCC_PCIE2_AUX_ARES 90
#define GCC_PCIE2_AXI_M_ARES 91
#define GCC_PCIE2_AXI_M_STICKY_ARES 92
#define GCC_PCIE2_AXI_S_ARES 93
#define GCC_PCIE2_AXI_S_STICKY_ARES 94
#define GCC_PCIE2_CORE_STICKY_ARES 95
#define GCC_PCIE2_PIPE_ARES 96
#define GCC_PCIE3_AHB_ARES 97
#define GCC_PCIE3_AUX_ARES 98
#define GCC_PCIE3_AXI_M_ARES 99
#define GCC_PCIE3_AXI_M_STICKY_ARES 100
#define GCC_PCIE3_AXI_S_ARES 101
#define GCC_PCIE3_AXI_S_STICKY_ARES 102
#define GCC_PCIE3_CORE_STICKY_ARES 103
#define GCC_PCIE3_PIPE_ARES 104
#define GCC_PCNOC_BCR 105
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115
#define GCC_PCNOC_TBU_BCR 116
#define GCC_Q6SS_DBG_ARES 117
#define GCC_Q6_AHB_ARES 118
#define GCC_Q6_AHB_S_ARES 119
#define GCC_Q6_AXIM2_ARES 120
#define GCC_Q6_AXIM_ARES 121
#define GCC_QDSS_BCR 122
#define GCC_QPIC_BCR 123
#define GCC_QPIC_AHB_ARES 124
#define GCC_QPIC_ARES 125
#define GCC_RBCPR_BCR 126
#define GCC_RBCPR_MX_BCR 127
#define GCC_SEC_CTRL_BCR 128
#define GCC_SMMU_CFG_BCR 129
#define GCC_SNOC_BCR 130
#define GCC_SPDM_BCR 131
#define GCC_TME_BCR 132
#define GCC_UNIPHY0_SYS_RESET 133
#define GCC_UNIPHY0_AHB_RESET 134
#define GCC_UNIPHY0_XPCS_RESET 135
#define GCC_UNIPHY1_SYS_RESET 136
#define GCC_UNIPHY1_AHB_RESET 137
#define GCC_UNIPHY1_XPCS_RESET 138
#define GCC_UNIPHY2_SYS_RESET 139
#define GCC_UNIPHY2_AHB_RESET 140
#define GCC_UNIPHY2_XPCS_RESET 141
#define GCC_USB_MISC_RESET 142
#define GCC_WCSSAON_RESET 143
#define GCC_WCSS_ACMT_ARES 144
#define GCC_WCSS_AHB_S_ARES 145
#define GCC_WCSS_AXI_M_ARES 146
#define GCC_WCSS_BCR 147
#define GCC_WCSS_DBG_ARES 148
#define GCC_WCSS_DBG_BDG_ARES 149
#define GCC_WCSS_ECAHB_ARES 150
#define GCC_WCSS_Q6_BCR 151
#define GCC_WCSS_Q6_TBU_BCR 152
#define GCC_TCSR_BCR 153
#endif