perf, x86: Avoid double disable on throttle vs ioctl(PERF_IOC_DISABLE)
Calling ioctl(PERF_EVENT_IOC_DISABLE) on a thottled counter would result in a double disable, cure this by using x86_pmu_{start,stop} for throttle/unthrottle and teach x86_pmu_stop() to check ->active_mask. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arnaldo Carvalho de Melo <acme@infradead.org> Cc: paulus@samba.org Cc: eranian@google.com Cc: robert.richter@amd.com Cc: fweisbec@gmail.com LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -983,14 +983,8 @@ static int x86_pmu_start(struct perf_event *event)
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static void x86_pmu_unthrottle(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
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cpuc->events[hwc->idx] != event))
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return;
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x86_pmu.enable(event);
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int ret = x86_pmu_start(event);
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WARN_ON_ONCE(ret);
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}
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void perf_event_print_debug(void)
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@ -1050,11 +1044,9 @@ static void x86_pmu_stop(struct perf_event *event)
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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/*
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* Must be done before we disable, otherwise the nmi handler
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* could reenable again:
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*/
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__clear_bit(idx, cpuc->active_mask);
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if (!__test_and_clear_bit(idx, cpuc->active_mask))
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return;
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x86_pmu.disable(event);
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/*
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@ -1123,7 +1115,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
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continue;
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if (perf_event_overflow(event, 1, &data, regs))
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x86_pmu.disable(event);
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x86_pmu_stop(event);
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}
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if (handled)
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@ -774,7 +774,7 @@ again:
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data.period = event->hw.last_period;
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if (perf_event_overflow(event, 1, &data, regs))
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intel_pmu_disable_event(event);
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x86_pmu_stop(event);
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}
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intel_pmu_ack_status(ack);
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