drm/amd/display: Fix HDMI VSIF V3 incorrect issue
[ Upstream commit 0591183699fceeafb4c4141072d47775de83ecfb ] [Why] Reported from customer the checksum in AMD VSIF V3 is incorrect and causing blank screen issue. [How] Fix the packet length issue on AMD HDMI VSIF V3. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -615,10 +615,6 @@ static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
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* Note: We should never go above the field rate of the mode timing set.
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*/
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infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
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/* FreeSync HDR */
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infopacket->sb[9] = 0;
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infopacket->sb[10] = 0;
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}
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static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
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@ -686,10 +682,6 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
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/* PB16 : Reserved bits 7:1, FixedRate bit 0 */
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infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
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//FreeSync HDR
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infopacket->sb[9] = 0;
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infopacket->sb[10] = 0;
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}
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static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
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@ -774,8 +766,7 @@ static void build_vrr_infopacket_header_v2(enum signal_type signal,
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/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
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infopacket->hb2 = 0x09;
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*payload_size = 0x0A;
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*payload_size = 0x09;
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} else if (dc_is_dp_signal(signal)) {
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/* HEADER */
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@ -824,9 +815,9 @@ static void build_vrr_infopacket_header_v3(enum signal_type signal,
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infopacket->hb1 = version;
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/* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */
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*payload_size = 0x10;
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infopacket->hb2 = *payload_size - 1; //-1 for checksum
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infopacket->hb2 = 0x10;
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*payload_size = 0x10;
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} else if (dc_is_dp_signal(signal)) {
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/* HEADER */
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