scsi: pm80xx: Fixed system hang issue during kexec boot
When the firmware is not responding, execution of kexec boot causes a system hang. When firmware assertion happened, driver get notified with interrupt vector updated in MPI configuration table. Then, the driver will read scratchpad register and set controller_fatal_error flag to true. Signed-off-by: Deepak Ukey <deepak.ukey@microchip.com> Signed-off-by: Viswas G <Viswas.G@microchip.com> Acked-by: Jack Wang <jinpu.wang@profitbricks.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Deepak Ukey
Martin K. Petersen
parent
76cb25b058
commit
72349b62a5
@ -1479,6 +1479,12 @@ u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
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} else {
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u32 producer_index;
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void *pi_virt = circularQ->pi_virt;
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/* spurious interrupt during setup if
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* kexec-ing and driver doing a doorbell access
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* with the pre-kexec oq interrupt setup
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*/
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if (!pi_virt)
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break;
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/* Update the producer index from SPC */
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producer_index = pm8001_read_32(pi_virt);
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circularQ->producer_index = cpu_to_le32(producer_index);
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@ -396,6 +396,13 @@ static int pm8001_task_exec(struct sas_task *task,
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return 0;
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}
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pm8001_ha = pm8001_find_ha_by_dev(task->dev);
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if (pm8001_ha->controller_fatal_error) {
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struct task_status_struct *ts = &t->task_status;
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ts->resp = SAS_TASK_UNDELIVERED;
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t->task_done(t);
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return 0;
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}
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PM8001_IO_DBG(pm8001_ha, pm8001_printk("pm8001_task_exec device \n "));
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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do {
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@ -538,6 +538,7 @@ struct pm8001_hba_info {
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u32 logging_level;
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u32 fw_status;
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u32 smp_exp_mode;
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bool controller_fatal_error;
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const struct firmware *fw_image;
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struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
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u32 reset_in_progress;
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@ -577,6 +577,9 @@ static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
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pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
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pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
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pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
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/* Update Fatal error interrupt vector */
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pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
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((pm8001_ha->number_of_intr - 1) << 8);
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pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
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pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
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pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
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@ -1110,6 +1113,9 @@ static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
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return -EBUSY;
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}
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/* Initialize the controller fatal error flag */
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pm8001_ha->controller_fatal_error = false;
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/* Initialize pci space address eg: mpi offset */
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init_pci_device_addresses(pm8001_ha);
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init_default_table_values(pm8001_ha);
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@ -1218,13 +1224,17 @@ pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
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u32 bootloader_state;
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u32 ibutton0, ibutton1;
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/* Check if MPI is in ready state to reset */
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if (mpi_uninit_check(pm8001_ha) != 0) {
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MPI state is not ready\n"));
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return -1;
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/* Process MPI table uninitialization only if FW is ready */
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if (!pm8001_ha->controller_fatal_error) {
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/* Check if MPI is in ready state to reset */
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if (mpi_uninit_check(pm8001_ha) != 0) {
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regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
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PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
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"MPI state is not ready scratch1 :0x%x\n",
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regval));
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return -1;
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}
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}
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/* checked for reset register normal state; 0x0 */
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regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
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PM8001_INIT_DBG(pm8001_ha,
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@ -3754,6 +3764,46 @@ static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
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}
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}
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static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
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{
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
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pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
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}
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static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
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{
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struct outbound_queue_table *circularQ;
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@ -3761,10 +3811,28 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
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u8 uninitialized_var(bc);
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u32 ret = MPI_IO_STATUS_FAIL;
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unsigned long flags;
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u32 regval;
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if (vec == (pm8001_ha->number_of_intr - 1)) {
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regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
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if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
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SCRATCH_PAD_MIPSALL_READY) {
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pm8001_ha->controller_fatal_error = true;
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PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
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"Firmware Fatal error! Regval:0x%x\n", regval));
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print_scratchpad_registers(pm8001_ha);
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return ret;
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}
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}
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spin_lock_irqsave(&pm8001_ha->lock, flags);
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circularQ = &pm8001_ha->outbnd_q_tbl[vec];
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do {
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/* spurious interrupt during setup if kexec-ing and
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* driver doing a doorbell access w/ the pre-kexec oq
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* interrupt setup.
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*/
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if (!circularQ->pi_virt)
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break;
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ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
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if (MPI_IO_STATUS_SUCCESS == ret) {
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/* process the outbound message */
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@ -1386,6 +1386,9 @@ typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
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#define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
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#define SCRATCH_PAD_IOP0_READY 0xC00
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#define SCRATCH_PAD_IOP1_READY 0x3000
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#define SCRATCH_PAD_MIPSALL_READY (SCRATCH_PAD_IOP1_READY | \
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SCRATCH_PAD_IOP0_READY | \
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SCRATCH_PAD_RAAE_READY)
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/* boot loader state */
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#define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
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