IB/mlx5: Fix scatter to CQE in DCT QP creation
When scatter to CQE is enabled on a DCT QP it corrupts the mailbox command
since it tried to treat it as as QP create mailbox command instead of a
DCT create command.
The corrupted mailbox command causes userspace to malfunction as the
device doesn't create the QP as expected.
A new mlx5 capability is exposed to user-space which ensures that it will
not enable the feature on DCT without this fix in the kernel.
Fixes: 5d6ff1babe
("IB/mlx5: Support scatter to CQE for DC transport type")
Signed-off-by: Guy Levi <guyle@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
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@ -1119,6 +1119,8 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
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if (MLX5_CAP_GEN(mdev, qp_packet_based))
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if (MLX5_CAP_GEN(mdev, qp_packet_based))
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resp.flags |=
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resp.flags |=
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MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
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MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
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resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
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}
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}
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if (field_avail(typeof(resp), sw_parsing_caps,
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if (field_avail(typeof(resp), sw_parsing_caps,
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@ -1818,13 +1818,16 @@ static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
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rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
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rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
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if (rcqe_sz == 128) {
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if (init_attr->qp_type == MLX5_IB_QPT_DCT) {
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MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
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if (rcqe_sz == 128)
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MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
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return;
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return;
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}
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}
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if (init_attr->qp_type != MLX5_IB_QPT_DCT)
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MLX5_SET(qpc, qpc, cs_res,
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MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
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rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
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MLX5_RES_SCAT_DATA32_CQE);
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}
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}
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static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
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static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
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@ -238,6 +238,7 @@ enum mlx5_ib_query_dev_resp_flags {
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
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MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
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MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
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MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
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};
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};
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enum mlx5_ib_tunnel_offloads {
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enum mlx5_ib_tunnel_offloads {
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