MIPS: Paravirt: remove remaining pieces of paravirt
Commit 35546aeede
("MIPS: Retire kvm paravirt") removed
kvm paravirt support, but missed arch/mips/include/mach-paravirt.
Remove it as well.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_tx39_cache 0
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#define cpu_has_counter 1
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#define cpu_has_llsc 1
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/*
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* We Disable LL/SC on non SMP systems as it is faster to disable
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* interrupts for atomic access than a LL/SC.
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*/
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#ifdef CONFIG_SMP
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# define kernel_uses_llsc 1
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#else
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# define kernel_uses_llsc 0
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#endif
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define cpu_dcache_line_size() 128
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#define cpu_icache_line_size() 128
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#define cpu_has_octeon_cache 1
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#define cpu_has_4k_cache 0
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#else
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#define cpu_has_4k_cache 1
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#endif
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#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#ifndef __ASM_MACH_PARAVIRT_IRQ_H__
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#define __ASM_MACH_PARAVIRT_IRQ_H__
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#define NR_IRQS 64
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#define MIPS_CPU_IRQ_BASE 1
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#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)
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#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
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#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)
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#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc
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*/
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#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
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#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
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#define CP0_EBASE $15, 1
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.macro kernel_entry_setup
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#ifdef CONFIG_SMP
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mfc0 t0, CP0_EBASE
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andi t0, t0, 0x3ff # CPUNum
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beqz t0, 1f
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# CPUs other than zero goto smp_bootstrap
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j smp_bootstrap
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#endif /* CONFIG_SMP */
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1:
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.endm
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/*
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* Do SMP slave processor setup necessary before we can safely execute
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* C code.
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*/
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.macro smp_slave_setup
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mfc0 t0, CP0_EBASE
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andi t0, t0, 0x3ff # CPUNum
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slti t1, t0, NR_CPUS
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bnez t1, 1f
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2:
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di
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wait
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b 2b # Unknown CPU, loop forever.
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1:
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PTR_LA t1, paravirt_smp_sp
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PTR_SLL t0, PTR_SCALESHIFT
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PTR_ADDU t1, t1, t0
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3:
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PTR_L sp, 0(t1)
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beqz sp, 3b # Spin until told to proceed.
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PTR_LA t1, paravirt_smp_gp
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PTR_ADDU t1, t1, t0
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sync
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PTR_L gp, 0(t1)
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.endm
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#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */
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