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clk: samsung: exynos5260: do not define number of clocks in bindings

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Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Krzysztof Kozlowski 2023-08-08 10:27:31 +02:00
parent 835dc5ac29
commit 727d0f0640
1 changed files with 28 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/clk/samsung/clk-exynos5260.c
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@ -15,6 +15,21 @@
#include <dt-bindings/clock/exynos5260-clk.h>
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1)
#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1)
#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
#define CLKS_NR_G3D (G3D_CLK_G3D + 1)
#define CLKS_NR_AUD (AUD_SCLK_I2S + 1)
#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1)
#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1)
#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1)
#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1)
#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1)
#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1)
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.nr_clk_ids = AUD_NR_CLK,
.nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
};
@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
.gate_clks = disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
.nr_clk_ids = DISP_NR_CLK,
.nr_clk_ids = CLKS_NR_DISP,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
};
@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
.div_clks = egl_div_clks,
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
.nr_clk_ids = EGL_NR_CLK,
.nr_clk_ids = CLKS_NR_EGL,
.clk_regs = egl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
};
@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = FSYS_NR_CLK,
.nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
};
@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
.nr_clk_ids = G2D_NR_CLK,
.nr_clk_ids = CLKS_NR_G2D,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
};
@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = G3D_NR_CLK,
.nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
};
@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
.nr_clk_ids = GSCL_NR_CLK,
.nr_clk_ids = CLKS_NR_GSCL,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
};
@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
.nr_clk_ids = ISP_NR_CLK,
.nr_clk_ids = CLKS_NR_ISP,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
};
@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
.div_clks = kfc_div_clks,
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
.nr_clk_ids = KFC_NR_CLK,
.nr_clk_ids = CLKS_NR_KFC,
.clk_regs = kfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
};
@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = MFC_NR_CLK,
.nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
.gate_clks = mif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
.nr_clk_ids = MIF_NR_CLK,
.nr_clk_ids = CLKS_NR_MIF,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
.nr_clk_ids = PERI_NR_CLK,
.nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
};
@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu __initconst = {
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.fixed_clks = fixed_rate_clks,
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
.nr_clk_ids = TOP_NR_CLK,
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};