drm/amdgpu/UAPI: rearrange header to better align related items
Move the RAS query parameters to align with the INFO query where they are used. No functional change. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -786,13 +786,6 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
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/* query ras mask of enabled features*/
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#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
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/* query video encode/decode caps */
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#define AMDGPU_INFO_VIDEO_CAPS 0x21
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/* Subquery id: Decode */
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#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
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/* Subquery id: Encode */
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#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
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/* RAS MASK: UMC (VRAM) */
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#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
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/* RAS MASK: SDMA */
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@ -821,6 +814,12 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
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/* RAS MASK: FUSE */
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#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
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/* query video encode/decode caps */
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#define AMDGPU_INFO_VIDEO_CAPS 0x21
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/* Subquery id: Decode */
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#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
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/* Subquery id: Encode */
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#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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