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drm/xe/mtl: Handle PAT_INDEX offset jump

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Starting with MTL, the number of entries in the PAT table increased to
16.  The register offset jumped between index 7 and index 8, so a slight
adjustment is needed to ensure the PAT_INDEX macros select the proper
offset for the upper half of the table.

Note that although there are 16 registers in the hardware, the driver is
currently only asked to program the first 5, and we leave the rest at
their hardware default values.  That means we don't actually touch the
upper half of the PAT table in the driver today and this patch won't
have any functional effect [yet].

Bspec: 44235
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-7-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-03-24 14:04:15 -07:00 committed by Rodrigo Vivi
parent f16a3f6335
commit 7321a713c6
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/xe/xe_pat.c
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@ -10,7 +10,9 @@
#include "xe_gt_mcr.h"
#include "xe_mmio.h"
#define _PAT_INDEX(index) (0x4800 + (index) * 4)
#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \
0x4800, 0x4804, \
0x4848, 0x484c)
#define MTL_L4_POLICY_MASK REG_GENMASK(3, 2)
#define MTL_PAT_3_UC REG_FIELD_PREP(MTL_L4_POLICY_MASK, 3)