iommu/amd: Introduce iommu_dev_data.ppr
For AMD IOMMU, the PPR feature is needed to support IO page fault (IOPF). PPR is enabled per PCI end-point device, and is configured by the PPR bit in the IOMMU device table entry (i.e DTE[PPR]). Introducing struct iommu_dev_data.ppr track PPR setting for each device. Also iommu_dev_data.ppr will be set only when IOMMU supports PPR. Hence remove redundant feature support check in set_dte_entry(). Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Co-developed-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Link: https://lore.kernel.org/r/20230921092147.5930-12-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -816,6 +816,7 @@ struct iommu_dev_data {
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u8 ats_enabled :1; /* ATS state */
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u8 pri_tlp :1; /* PASID TLB required for
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PPR completions */
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u8 ppr :1; /* Enable device PPR support */
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bool use_vapic; /* Enable device to use vapic mode */
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bool defer_attach;
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@ -1638,10 +1638,8 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
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if (ats)
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flags |= DTE_FLAG_IOTLB;
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if (ppr) {
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if (check_feature(FEATURE_EPHSUP))
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pte_root |= 1ULL << DEV_ENTRY_PPR;
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}
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if (ppr)
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pte_root |= 1ULL << DEV_ENTRY_PPR;
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if (domain->flags & PD_IOMMUV2_MASK) {
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u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
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@ -1734,7 +1732,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
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/* Update device table */
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set_dte_entry(iommu, dev_data->devid, domain,
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ats, dev_data->iommu_v2);
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ats, dev_data->ppr);
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clone_aliases(iommu, dev_data->dev);
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device_flush_dte(dev_data);
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@ -2013,7 +2011,7 @@ static void update_device_table(struct protection_domain *domain)
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if (!iommu)
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continue;
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set_dte_entry(iommu, dev_data->devid, domain,
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dev_data->ats_enabled, dev_data->iommu_v2);
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dev_data->ats_enabled, dev_data->ppr);
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clone_aliases(iommu, dev_data->dev);
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}
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}
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