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soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()

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Add missing iounmap() before return error from sifive_ccache_init().

Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Yang Yingliang 2022-10-18 10:31:47 +08:00 committed by Conor Dooley
parent 9abf2313ad
commit 73e770f085
1 changed files with 11 additions and 4 deletions
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15
drivers/soc/sifive/sifive_ccache.c
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@ -222,13 +222,16 @@ static int __init sifive_ccache_init(void)
if (!ccache_base)
return -ENOMEM;
if (of_property_read_u32(np, "cache-level", &level))
return -ENOENT;
if (of_property_read_u32(np, "cache-level", &level)) {
rc = -ENOENT;
goto err_unmap;
}
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("No interrupts property\n");
return -ENODEV;
rc = -ENODEV;
goto err_unmap;
}
for (i = 0; i < intr_num; i++) {
@ -237,7 +240,7 @@ static int __init sifive_ccache_init(void)
NULL);
if (rc) {
pr_err("Could not request IRQ %d\n", g_irq[i]);
return rc;
goto err_unmap;
}
}
@ -250,6 +253,10 @@ static int __init sifive_ccache_init(void)
setup_sifive_debug();
#endif
return 0;
err_unmap:
iounmap(ccache_base);
return rc;
}
device_initcall(sifive_ccache_init);