KVM: x86: move MSR_IA32_POWER_CTL handling to common code
Make it available to AMD hosts as well, just in case someone is trying to use an Intel processor's CPUID setup. Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -689,6 +689,7 @@ struct kvm_vcpu_arch {
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u32 virtual_tsc_mult;
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u32 virtual_tsc_khz;
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s64 ia32_tsc_adjust_msr;
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u64 msr_ia32_power_ctl;
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u64 tsc_scaling_ratio;
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atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
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@ -1695,9 +1695,6 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_SYSENTER_ESP:
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msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
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break;
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case MSR_IA32_POWER_CTL:
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msr_info->data = vmx->msr_ia32_power_ctl;
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break;
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case MSR_IA32_BNDCFGS:
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if (!kvm_mpx_supported() ||
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(!msr_info->host_initiated &&
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@ -1828,9 +1825,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_SYSENTER_ESP:
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vmcs_writel(GUEST_SYSENTER_ESP, data);
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break;
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case MSR_IA32_POWER_CTL:
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vmx->msr_ia32_power_ctl = data;
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break;
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case MSR_IA32_BNDCFGS:
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if (!kvm_mpx_supported() ||
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(!msr_info->host_initiated &&
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@ -260,8 +260,6 @@ struct vcpu_vmx {
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unsigned long host_debugctlmsr;
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u64 msr_ia32_power_ctl;
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/*
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* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
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* msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
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@ -2563,6 +2563,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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vcpu->arch.smbase = data;
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break;
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case MSR_IA32_POWER_CTL:
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vcpu->arch.msr_ia32_power_ctl = data;
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break;
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case MSR_IA32_TSC:
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kvm_write_tsc(vcpu, msr_info);
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break;
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@ -2822,6 +2825,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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msr_info->data = vcpu->arch.arch_capabilities;
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break;
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case MSR_IA32_POWER_CTL:
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msr_info->data = vcpu->arch.msr_ia32_power_ctl;
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break;
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case MSR_IA32_TSC:
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msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
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break;
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