dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
Add device tree binding Documentation details for Qualcomm SDX65 pinctrl driver. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/ff9abf953c274a1e34f59114642f67ecf02acb6f.1639696427.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Vamsi Krishna Lanka
Linus Walleij
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SDX65 TLMM block
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maintainers:
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- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
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description:
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This binding describes the Top Level Mode Multiplexer block found in the
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SDX65 platform.
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properties:
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compatible:
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const: qcom,sdx65-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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description: Specifies the PIN numbers and Flags, as defined in
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include/dt-bindings/interrupt-controller/irq.h
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const: 2
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gpio-controller: true
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'#gpio-cells':
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description: Specifying the pin number and flags, as defined in
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include/dt-bindings/gpio/gpio.h
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const: 2
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gpio-ranges:
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maxItems: 1
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gpio-reserved-ranges:
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maxItems: 1
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#PIN CONFIGURATION NODES
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patternProperties:
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'-state$':
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oneOf:
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- $ref: "#/$defs/qcom-sdx65-tlmm-state"
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- patternProperties:
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".*":
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$ref: "#/$defs/qcom-sdx65-tlmm-state"
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'$defs':
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qcom-sdx65-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
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- enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
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minItems: 1
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maxItems: 150
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins. Functions are only valid for gpio pins.
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enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
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bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
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qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
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dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
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blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
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mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
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atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
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cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
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pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
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qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
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qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
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atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
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atest_usb20, atest_char0, dac_calib10, qdss_stm10,
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qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
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blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
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qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
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qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
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dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
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qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
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dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
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dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
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dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
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dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
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sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
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qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
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uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
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blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
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qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
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blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
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cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
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blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
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qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
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isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
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qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
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sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
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gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
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qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
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tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
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qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
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sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
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sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
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ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
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blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
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pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
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qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
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qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
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gpio ]
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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default: 2
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description:
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Selects the drive strength for the specified pins, in mA.
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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output-high: true
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output-low: true
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required:
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- pins
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- function
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sdx65-tlmm";
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reg = <0x03000000 0xdc2000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 109>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-subnode-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-subnodes-state {
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rx {
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pins = "gpio4";
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function = "blsp_uart1";
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bias-pull-up;
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};
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tx {
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pins = "gpio5";
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function = "blsp_uart1";
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bias-disable;
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};
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};
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};
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...
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