MIPS: OCTEON: octeon-usb: use bitfields for host config register
Use Linux standard bitfield access macros to manipulate host config register. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -126,47 +126,36 @@
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#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port))
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/*
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* UCTL Configuration Register
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*/
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#define USBDRD_UCTL_HOST_CFG 0xe0
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/* Indicates minimum value of all received BELT values */
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# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48)
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/* HS jitter adjustment */
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# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32)
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/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
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# define USBDRD_UCTL_HOST_CFG_BME BIT(28)
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/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
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# define USBDRD_UCTL_HOST_OCI_EN BIT(27)
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/* Overcurrent sene selection:
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* 0x0 = Overcurrent indication from off-chip is active-low
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* 0x1 = Overcurrent indication from off-chip is active-high
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*/
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# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26)
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/* Port power control enable: 0x0 = unavailable, 0x1 = available */
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# define USBDRD_UCTL_HOST_PPC_EN BIT(25)
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/* Port power control sense selection:
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* 0x0 = Port power to off-chip is active-low
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* 0x1 = Port power to off-chip is active-high
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*/
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# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24)
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#define USBDRD_UCTL_SHIM_CFG 0xe8
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8
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/* UAHC Configuration Register */
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union cvm_usbdrd_uctl_host_cfg {
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uint64_t u64;
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struct cvm_usbdrd_uctl_host_cfg_s {
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_60_63:4,
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/* Indicates minimum value of all received BELT values */
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__BITFIELD_FIELD(uint64_t host_current_belt:12,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_38_47:10,
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/* HS jitter adjustment */
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__BITFIELD_FIELD(uint64_t fla:6,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_29_31:3,
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/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
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__BITFIELD_FIELD(uint64_t bme:1,
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/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
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__BITFIELD_FIELD(uint64_t oci_en:1,
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/* Overcurrent sene selection:
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* 0x0 = Overcurrent indication from off-chip is active-low
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* 0x1 = Overcurrent indication from off-chip is active-high
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*/
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__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
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/* Port power control enable: 0x0 = unavailable, 0x1 = available */
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__BITFIELD_FIELD(uint64_t ppc_en:1,
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/* Port power control sense selection:
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* 0x0 = Port power to off-chip is active-low
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* 0x1 = Port power to off-chip is active-high
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*/
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__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_0_23:24,
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;)))))))))))
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} s;
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};
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/* UCTL Shim Features Register */
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union cvm_usbdrd_uctl_shim_cfg {
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uint64_t u64;
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@ -224,12 +213,13 @@ static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
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static int dwc3_octeon_config_power(struct device *dev, u64 base)
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{
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union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
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union cvmx_gpio_bit_cfgx gpio_bit;
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uint32_t gpio_pwr[3];
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int gpio, len, power_active_low;
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struct device_node *node = dev->of_node;
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int index = (base >> 24) & 1;
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u64 val;
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u64 uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
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if (of_find_property(node, "power", &len) != NULL) {
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if (len == 12) {
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@ -264,16 +254,19 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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}
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/* Enable XHCI power control and set if active high or low. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 1;
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uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
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cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64);
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val = cvmx_read_csr(uctl_host_cfg_reg);
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val |= USBDRD_UCTL_HOST_PPC_EN;
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if (power_active_low)
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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else
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val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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cvmx_write_csr(uctl_host_cfg_reg, val);
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} else {
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/* Disable XHCI power control and set if active high. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 0;
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uctl_host_cfg.s.ppc_active_high_en = 0;
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cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64);
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val = cvmx_read_csr(uctl_host_cfg_reg);
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val &= ~USBDRD_UCTL_HOST_PPC_EN;
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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cvmx_write_csr(uctl_host_cfg_reg, val);
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dev_info(dev, "power control disabled\n");
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}
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return 0;
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