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phy: qcom-qmp: clean up v4 and v5 define order

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Clean up the QMP v4 and v5 defines by moving a few entries that were out
of order.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220609120338.4080-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Johan Hovold 2022-06-09 14:03:36 +02:00 committed by Vinod Koul
parent 5d5b7d509f
commit 74acf0ee6e
1 changed files with 3 additions and 3 deletions
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6
drivers/phy/qualcomm/phy-qcom-qmp.h
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@ -577,8 +577,8 @@
#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
@ -1093,8 +1093,8 @@
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
@ -1121,8 +1121,8 @@
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
/* Only for QMP V5 PHY - TX registers */ /* Only for QMP V5 PHY - TX registers */
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34