iwlwifi: move agn only tx functions from iwlcore to iwlagn
Identify the tx functions only used by agn driver and move those from iwlcore to iwlagn. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
This commit is contained in:
parent
348ee7cd57
commit
74bcdb33e9
@ -46,6 +46,7 @@
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#include "iwl-calib.h"
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#include "iwl-calib.h"
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#include "iwl-sta.h"
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#include "iwl-sta.h"
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#include "iwl-agn-led.h"
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#include "iwl-agn-led.h"
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#include "iwl-agn.h"
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static int iwl4965_send_tx_power(struct iwl_priv *priv);
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static int iwl4965_send_tx_power(struct iwl_priv *priv);
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static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
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static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
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@ -2020,7 +2021,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
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index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
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index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
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IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
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IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
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"%d index %d\n", scd_ssn , index);
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"%d index %d\n", scd_ssn , index);
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freed = iwl_tx_queue_reclaim(priv, txq_id, index);
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freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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if (priv->mac80211_registered &&
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if (priv->mac80211_registered &&
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@ -2046,7 +2047,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
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le32_to_cpu(tx_resp->rate_n_flags),
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le32_to_cpu(tx_resp->rate_n_flags),
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tx_resp->failure_frame);
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tx_resp->failure_frame);
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freed = iwl_tx_queue_reclaim(priv, txq_id, index);
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freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
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if (qc && likely(sta_id != IWL_INVALID_STATION))
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if (qc && likely(sta_id != IWL_INVALID_STATION))
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priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
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priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
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@ -2056,7 +2057,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
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}
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}
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if (qc && likely(sta_id != IWL_INVALID_STATION))
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if (qc && likely(sta_id != IWL_INVALID_STATION))
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iwl_txq_check_empty(priv, sta_id, tid, txq_id);
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iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
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if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
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if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
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IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
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IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
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@ -208,7 +208,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
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"scd_ssn=%d idx=%d txq=%d swq=%d\n",
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"scd_ssn=%d idx=%d txq=%d swq=%d\n",
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scd_ssn , index, txq_id, txq->swq_id);
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scd_ssn , index, txq_id, txq->swq_id);
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freed = iwl_tx_queue_reclaim(priv, txq_id, index);
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freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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if (priv->mac80211_registered &&
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if (priv->mac80211_registered &&
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@ -236,7 +236,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
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le32_to_cpu(tx_resp->rate_n_flags),
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le32_to_cpu(tx_resp->rate_n_flags),
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tx_resp->failure_frame);
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tx_resp->failure_frame);
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freed = iwl_tx_queue_reclaim(priv, txq_id, index);
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freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
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if (priv->mac80211_registered &&
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if (priv->mac80211_registered &&
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@ -244,7 +244,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
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iwl_wake_queue(priv, txq_id);
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iwl_wake_queue(priv, txq_id);
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}
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}
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iwl_txq_check_empty(priv, sta_id, tid, txq_id);
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iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
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if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
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if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
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IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
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IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
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@ -381,3 +381,133 @@ struct iwl_mod_params iwlagn_mod_params = {
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.restart_fw = 1,
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.restart_fw = 1,
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/* the rest are 0 by default */
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/* the rest are 0 by default */
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};
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};
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void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&rxq->lock, flags);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
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/* In the reset function, these buffers may have been allocated
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* to an SKB, so we need to unmap and free potential storage */
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if (rxq->pool[i].page != NULL) {
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pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
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PAGE_SIZE << priv->hw_params.rx_page_order,
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PCI_DMA_FROMDEVICE);
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__iwl_free_pages(priv, rxq->pool[i].page);
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rxq->pool[i].page = NULL;
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}
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list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
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}
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/* Set us so that we have processed and used all buffers, but have
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* not restocked the Rx queue with fresh buffers */
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rxq->read = rxq->write = 0;
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rxq->write_actual = 0;
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rxq->free_count = 0;
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spin_unlock_irqrestore(&rxq->lock, flags);
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}
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int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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u32 rb_size;
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
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if (!priv->cfg->use_isr_legacy)
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rb_timeout = RX_RB_TIMEOUT;
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if (priv->cfg->mod_params->amsdu_size_8K)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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else
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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/* Stop Rx DMA */
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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/* Reset driver's Rx queue write index */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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/* Tell device where to find RBD circular buffer in DRAM */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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(u32)(rxq->dma_addr >> 8));
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/* Tell device where in DRAM to update its Rx status */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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rxq->rb_stts_dma >> 4);
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/* Enable Rx DMA
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
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* the credit mechanism in 5000 HW RX FIFO
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* Direct rx interrupts to hosts
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* Rx buffer size 4 or 8k
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* RB timeout 0x10
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* 256 RBDs
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*/
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
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rb_size|
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(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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/* Set interrupt coalescing timer to default (2048 usecs) */
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iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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return 0;
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}
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int iwlagn_hw_nic_init(struct iwl_priv *priv)
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{
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unsigned long flags;
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struct iwl_rx_queue *rxq = &priv->rxq;
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int ret;
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/* nic_init */
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spin_lock_irqsave(&priv->lock, flags);
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priv->cfg->ops->lib->apm_ops.init(priv);
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/* Set interrupt coalescing calibration timer to default (512 usecs) */
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iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
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spin_unlock_irqrestore(&priv->lock, flags);
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ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
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priv->cfg->ops->lib->apm_ops.config(priv);
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/* Allocate the RX queue, or reset if it is already allocated */
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if (!rxq->bd) {
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ret = iwl_rx_queue_alloc(priv);
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if (ret) {
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IWL_ERR(priv, "Unable to initialize Rx queue\n");
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return -ENOMEM;
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}
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} else
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iwlagn_rx_queue_reset(priv, rxq);
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iwl_rx_replenish(priv);
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iwlagn_rx_init(priv, rxq);
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spin_lock_irqsave(&priv->lock, flags);
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rxq->need_update = 1;
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iwl_rx_queue_update_write_ptr(priv, rxq);
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spin_unlock_irqrestore(&priv->lock, flags);
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/* Allocate and init all Tx and Command queues */
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ret = iwlagn_txq_ctx_reset(priv);
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if (ret)
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return ret;
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set_bit(STATUS_INIT, &priv->status);
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return 0;
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}
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File diff suppressed because it is too large
Load Diff
@ -887,7 +887,7 @@ static void iwl_setup_rx_handlers(struct iwl_priv *priv)
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priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
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priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
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priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
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priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
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/* block ack */
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/* block ack */
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priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
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priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
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/* Set up hardware specific Rx handlers */
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/* Set up hardware specific Rx handlers */
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priv->cfg->ops->lib->rx_handler_setup(priv);
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priv->cfg->ops->lib->rx_handler_setup(priv);
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}
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}
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@ -2249,7 +2249,7 @@ static void __iwl_down(struct iwl_priv *priv)
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/* device going down, Stop using ICT table */
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/* device going down, Stop using ICT table */
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iwl_disable_ict(priv);
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iwl_disable_ict(priv);
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iwl_txq_ctx_stop(priv);
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iwlagn_txq_ctx_stop(priv);
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iwl_rxq_stop(priv);
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iwl_rxq_stop(priv);
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/* Power-down device's busmaster DMA clocks */
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/* Power-down device's busmaster DMA clocks */
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@ -2371,7 +2371,7 @@ static int __iwl_up(struct iwl_priv *priv)
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iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
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iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
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ret = iwl_hw_nic_init(priv);
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ret = iwlagn_hw_nic_init(priv);
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if (ret) {
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if (ret) {
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IWL_ERR(priv, "Unable to init nic\n");
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IWL_ERR(priv, "Unable to init nic\n");
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return ret;
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return ret;
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@ -2782,7 +2782,7 @@ static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
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IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
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IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
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ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
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ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
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if (iwl_tx_skb(priv, skb))
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if (iwlagn_tx_skb(priv, skb))
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dev_kfree_skb_any(skb);
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dev_kfree_skb_any(skb);
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IWL_DEBUG_MACDUMP(priv, "leave\n");
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IWL_DEBUG_MACDUMP(priv, "leave\n");
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@ -2970,7 +2970,7 @@ static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
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return ret;
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return ret;
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case IEEE80211_AMPDU_TX_START:
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case IEEE80211_AMPDU_TX_START:
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IWL_DEBUG_HT(priv, "start Tx\n");
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IWL_DEBUG_HT(priv, "start Tx\n");
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ret = iwl_tx_agg_start(priv, sta->addr, tid, ssn);
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ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
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if (ret == 0) {
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if (ret == 0) {
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priv->_agn.agg_tids_count++;
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priv->_agn.agg_tids_count++;
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IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
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IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
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@ -2979,7 +2979,7 @@ static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
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return ret;
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return ret;
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case IEEE80211_AMPDU_TX_STOP:
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case IEEE80211_AMPDU_TX_STOP:
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IWL_DEBUG_HT(priv, "stop Tx\n");
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IWL_DEBUG_HT(priv, "stop Tx\n");
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ret = iwl_tx_agg_stop(priv, sta->addr, tid);
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ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
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if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
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if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
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priv->_agn.agg_tids_count--;
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priv->_agn.agg_tids_count--;
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IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
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IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
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@ -3738,7 +3738,7 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
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if (priv->rxq.bd)
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if (priv->rxq.bd)
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iwl_rx_queue_free(priv, &priv->rxq);
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iwl_rx_queue_free(priv, &priv->rxq);
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iwl_hw_txq_ctx_free(priv);
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iwlagn_hw_txq_ctx_free(priv);
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iwl_eeprom_free(priv);
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iwl_eeprom_free(priv);
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@ -113,5 +113,22 @@ void iwlagn_temperature(struct iwl_priv *priv);
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u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv);
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u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv);
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const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
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const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
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size_t offset);
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size_t offset);
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void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
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int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
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int iwlagn_hw_nic_init(struct iwl_priv *priv);
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/* tx */
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int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb);
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int iwlagn_tx_agg_start(struct iwl_priv *priv,
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const u8 *ra, u16 tid, u16 *ssn);
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int iwlagn_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid);
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int iwlagn_txq_check_empty(struct iwl_priv *priv,
|
||||||
|
int sta_id, u8 tid, int txq_id);
|
||||||
|
void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
|
||||||
|
struct iwl_rx_mem_buffer *rxb);
|
||||||
|
int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
|
||||||
|
void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv);
|
||||||
|
int iwlagn_txq_ctx_reset(struct iwl_priv *priv);
|
||||||
|
void iwlagn_txq_ctx_stop(struct iwl_priv *priv);
|
||||||
|
|
||||||
#endif /* __iwl_agn_h__ */
|
#endif /* __iwl_agn_h__ */
|
||||||
|
@ -265,57 +265,6 @@ void iwl_hw_detect(struct iwl_priv *priv)
|
|||||||
}
|
}
|
||||||
EXPORT_SYMBOL(iwl_hw_detect);
|
EXPORT_SYMBOL(iwl_hw_detect);
|
||||||
|
|
||||||
int iwl_hw_nic_init(struct iwl_priv *priv)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
struct iwl_rx_queue *rxq = &priv->rxq;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
/* nic_init */
|
|
||||||
spin_lock_irqsave(&priv->lock, flags);
|
|
||||||
priv->cfg->ops->lib->apm_ops.init(priv);
|
|
||||||
|
|
||||||
/* Set interrupt coalescing calibration timer to default (512 usecs) */
|
|
||||||
iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&priv->lock, flags);
|
|
||||||
|
|
||||||
ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
|
|
||||||
|
|
||||||
priv->cfg->ops->lib->apm_ops.config(priv);
|
|
||||||
|
|
||||||
/* Allocate the RX queue, or reset if it is already allocated */
|
|
||||||
if (!rxq->bd) {
|
|
||||||
ret = iwl_rx_queue_alloc(priv);
|
|
||||||
if (ret) {
|
|
||||||
IWL_ERR(priv, "Unable to initialize Rx queue\n");
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
} else
|
|
||||||
iwl_rx_queue_reset(priv, rxq);
|
|
||||||
|
|
||||||
iwl_rx_replenish(priv);
|
|
||||||
|
|
||||||
iwl_rx_init(priv, rxq);
|
|
||||||
|
|
||||||
spin_lock_irqsave(&priv->lock, flags);
|
|
||||||
|
|
||||||
rxq->need_update = 1;
|
|
||||||
iwl_rx_queue_update_write_ptr(priv, rxq);
|
|
||||||
|
|
||||||
spin_unlock_irqrestore(&priv->lock, flags);
|
|
||||||
|
|
||||||
/* Allocate and init all Tx and Command queues */
|
|
||||||
ret = iwl_txq_ctx_reset(priv);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
set_bit(STATUS_INIT, &priv->status);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(iwl_hw_nic_init);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* QoS support
|
* QoS support
|
||||||
*/
|
*/
|
||||||
|
@ -336,7 +336,6 @@ void iwl_irq_handle_error(struct iwl_priv *priv);
|
|||||||
void iwl_configure_filter(struct ieee80211_hw *hw,
|
void iwl_configure_filter(struct ieee80211_hw *hw,
|
||||||
unsigned int changed_flags,
|
unsigned int changed_flags,
|
||||||
unsigned int *total_flags, u64 multicast);
|
unsigned int *total_flags, u64 multicast);
|
||||||
int iwl_hw_nic_init(struct iwl_priv *priv);
|
|
||||||
int iwl_set_hw_params(struct iwl_priv *priv);
|
int iwl_set_hw_params(struct iwl_priv *priv);
|
||||||
bool iwl_is_monitor_mode(struct iwl_priv *priv);
|
bool iwl_is_monitor_mode(struct iwl_priv *priv);
|
||||||
void iwl_post_associate(struct iwl_priv *priv);
|
void iwl_post_associate(struct iwl_priv *priv);
|
||||||
@ -426,15 +425,12 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv);
|
|||||||
void iwl_rx_handle(struct iwl_priv *priv);
|
void iwl_rx_handle(struct iwl_priv *priv);
|
||||||
void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
|
void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
|
||||||
struct iwl_rx_queue *q);
|
struct iwl_rx_queue *q);
|
||||||
void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
|
|
||||||
void iwl_rx_replenish(struct iwl_priv *priv);
|
void iwl_rx_replenish(struct iwl_priv *priv);
|
||||||
void iwl_rx_replenish_now(struct iwl_priv *priv);
|
void iwl_rx_replenish_now(struct iwl_priv *priv);
|
||||||
int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
|
|
||||||
void iwl_rx_queue_restock(struct iwl_priv *priv);
|
void iwl_rx_queue_restock(struct iwl_priv *priv);
|
||||||
int iwl_rx_queue_space(const struct iwl_rx_queue *q);
|
int iwl_rx_queue_space(const struct iwl_rx_queue *q);
|
||||||
void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority);
|
void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority);
|
||||||
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
|
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
|
||||||
int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
|
|
||||||
/* Handlers */
|
/* Handlers */
|
||||||
void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
|
void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
|
||||||
struct iwl_rx_mem_buffer *rxb);
|
struct iwl_rx_mem_buffer *rxb);
|
||||||
@ -455,13 +451,10 @@ void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
|
|||||||
/*****************************************************
|
/*****************************************************
|
||||||
* TX
|
* TX
|
||||||
******************************************************/
|
******************************************************/
|
||||||
int iwl_txq_ctx_reset(struct iwl_priv *priv);
|
|
||||||
void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
|
void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq);
|
||||||
int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
|
int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
|
||||||
struct iwl_tx_queue *txq,
|
struct iwl_tx_queue *txq,
|
||||||
dma_addr_t addr, u16 len, u8 reset, u8 pad);
|
dma_addr_t addr, u16 len, u8 reset, u8 pad);
|
||||||
int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb);
|
|
||||||
void iwl_hw_txq_ctx_free(struct iwl_priv *priv);
|
|
||||||
int iwl_hw_tx_queue_init(struct iwl_priv *priv,
|
int iwl_hw_tx_queue_init(struct iwl_priv *priv,
|
||||||
struct iwl_tx_queue *txq);
|
struct iwl_tx_queue *txq);
|
||||||
void iwl_free_tfds_in_queue(struct iwl_priv *priv,
|
void iwl_free_tfds_in_queue(struct iwl_priv *priv,
|
||||||
@ -470,9 +463,6 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
|
|||||||
int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
|
int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
|
||||||
int slots_num, u32 txq_id);
|
int slots_num, u32 txq_id);
|
||||||
void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id);
|
void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id);
|
||||||
int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn);
|
|
||||||
int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid);
|
|
||||||
int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id);
|
|
||||||
/*****************************************************
|
/*****************************************************
|
||||||
* TX power
|
* TX power
|
||||||
****************************************************/
|
****************************************************/
|
||||||
@ -689,8 +679,6 @@ extern void iwl_rx_reply_rx(struct iwl_priv *priv,
|
|||||||
struct iwl_rx_mem_buffer *rxb);
|
struct iwl_rx_mem_buffer *rxb);
|
||||||
extern void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
|
extern void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
|
||||||
struct iwl_rx_mem_buffer *rxb);
|
struct iwl_rx_mem_buffer *rxb);
|
||||||
void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
|
|
||||||
struct iwl_rx_mem_buffer *rxb);
|
|
||||||
void iwl_apm_stop(struct iwl_priv *priv);
|
void iwl_apm_stop(struct iwl_priv *priv);
|
||||||
int iwl_apm_init(struct iwl_priv *priv);
|
int iwl_apm_init(struct iwl_priv *priv);
|
||||||
|
|
||||||
|
@ -35,6 +35,7 @@ EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_iowrite8);
|
|||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ioread32);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ioread32);
|
||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_iowrite32);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_iowrite32);
|
||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_rx);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_rx);
|
||||||
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_tx);
|
||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_event);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_event);
|
||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_error);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_error);
|
||||||
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_cont_event);
|
EXPORT_TRACEPOINT_SYMBOL(iwlwifi_dev_ucode_cont_event);
|
||||||
|
@ -395,86 +395,6 @@ err_bd:
|
|||||||
}
|
}
|
||||||
EXPORT_SYMBOL(iwl_rx_queue_alloc);
|
EXPORT_SYMBOL(iwl_rx_queue_alloc);
|
||||||
|
|
||||||
void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
int i;
|
|
||||||
spin_lock_irqsave(&rxq->lock, flags);
|
|
||||||
INIT_LIST_HEAD(&rxq->rx_free);
|
|
||||||
INIT_LIST_HEAD(&rxq->rx_used);
|
|
||||||
/* Fill the rx_used queue with _all_ of the Rx buffers */
|
|
||||||
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
|
|
||||||
/* In the reset function, these buffers may have been allocated
|
|
||||||
* to an SKB, so we need to unmap and free potential storage */
|
|
||||||
if (rxq->pool[i].page != NULL) {
|
|
||||||
pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
|
|
||||||
PAGE_SIZE << priv->hw_params.rx_page_order,
|
|
||||||
PCI_DMA_FROMDEVICE);
|
|
||||||
__iwl_free_pages(priv, rxq->pool[i].page);
|
|
||||||
rxq->pool[i].page = NULL;
|
|
||||||
}
|
|
||||||
list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set us so that we have processed and used all buffers, but have
|
|
||||||
* not restocked the Rx queue with fresh buffers */
|
|
||||||
rxq->read = rxq->write = 0;
|
|
||||||
rxq->write_actual = 0;
|
|
||||||
rxq->free_count = 0;
|
|
||||||
spin_unlock_irqrestore(&rxq->lock, flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
|
|
||||||
{
|
|
||||||
u32 rb_size;
|
|
||||||
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
|
|
||||||
u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
|
|
||||||
|
|
||||||
if (!priv->cfg->use_isr_legacy)
|
|
||||||
rb_timeout = RX_RB_TIMEOUT;
|
|
||||||
|
|
||||||
if (priv->cfg->mod_params->amsdu_size_8K)
|
|
||||||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
|
|
||||||
else
|
|
||||||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
|
|
||||||
|
|
||||||
/* Stop Rx DMA */
|
|
||||||
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
|
|
||||||
|
|
||||||
/* Reset driver's Rx queue write index */
|
|
||||||
iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
|
|
||||||
|
|
||||||
/* Tell device where to find RBD circular buffer in DRAM */
|
|
||||||
iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
|
|
||||||
(u32)(rxq->dma_addr >> 8));
|
|
||||||
|
|
||||||
/* Tell device where in DRAM to update its Rx status */
|
|
||||||
iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
|
|
||||||
rxq->rb_stts_dma >> 4);
|
|
||||||
|
|
||||||
/* Enable Rx DMA
|
|
||||||
* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
|
|
||||||
* the credit mechanism in 5000 HW RX FIFO
|
|
||||||
* Direct rx interrupts to hosts
|
|
||||||
* Rx buffer size 4 or 8k
|
|
||||||
* RB timeout 0x10
|
|
||||||
* 256 RBDs
|
|
||||||
*/
|
|
||||||
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
|
|
||||||
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
|
|
||||||
FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
|
|
||||||
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
|
|
||||||
FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
|
|
||||||
rb_size|
|
|
||||||
(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
|
|
||||||
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
|
|
||||||
|
|
||||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
|
||||||
iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int iwl_rxq_stop(struct iwl_priv *priv)
|
int iwl_rxq_stop(struct iwl_priv *priv)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
@ -1395,6 +1395,7 @@ void iwl_sta_modify_sleep_tx_count(struct iwl_priv *priv, int sta_id, int cnt)
|
|||||||
|
|
||||||
iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
|
iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL(iwl_sta_modify_sleep_tx_count);
|
||||||
|
|
||||||
int iwl_mac_sta_remove(struct ieee80211_hw *hw,
|
int iwl_mac_sta_remove(struct ieee80211_hw *hw,
|
||||||
struct ieee80211_vif *vif,
|
struct ieee80211_vif *vif,
|
||||||
|
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user