iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ASoC: SOF: Intel: MTL: Don't access EM2

Browse Source 
This reverts commit 2b5a30cafb2ef ("ASoC: SOF: Intel: MTL: Enable
DMI L1").

It came to our attention that the access to the EM2 register is restricted
to the DSP side on MTL compared to prior platforms.

Writing to it from the host side has no effect (negative or positive), it
is better to remove the code to not cause confusion and wrong impression.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230310133454.15362-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Peter Ujfalusi 2023-03-10 15:34:54 +02:00 committed by Mark Brown
parent 8987986b07
commit 75034eb5e4
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 0 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sound/soc/sof/intel/mtl.c
View File

@ -280,9 +280,6 @@ static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
}
hda_sdw_int_enable(sdev, true);
/* enable DMI L1 */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_EM2, MTL_EM2_L1SEN, MTL_EM2_L1SEN);
return 0;
}

2
sound/soc/sof/intel/mtl.h
View File

@ -28,8 +28,6 @@
#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0)
#define MTL_HDA_VS_D0I3C 0x1D4A
#define MTL_EM2 0x1c44
#define MTL_EM2_L1SEN BIT(13)
#define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00
#define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04