powerpc fixes for 4.8 #7
- powernv/pci: Fix m64 checks for SR-IOV and window alignment from Russell Currey -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX50CvAAoJEFHr6jzI4aWAqJAP/0/0D8YGwOuIoYD2GmfoasKR TFbbuhX3xnfdiRG6w/sFBI3oh7icCw7hC+Qj1lNu9D3L/UkxOTBny+W07KvWzX44 Yu74nEHgq3mVrRAU4McztbKIUBK2zagGwwCcGZXZl/uQI1ylvmmpcH3xClQzF+oA xKk8eB1OW2Ay6+y+FkSuyBHHSfww6QCk7ERPqaStCW9Uy+dDBjIwStLQuOpAhN/o Z9K+JwpPJ8qgw1Pe9pvrD5MjcM0hR+tUZm6LklZCCk89feqlwcrz9cpOrmTdGuF+ n1iacpDaFf6IOlhI+6ImrT15llTgSk/nu9GNIRFDwOjVCuGy5aDQBtWuRFiVNggp vkZWFSl594Jn5H9/s6MpMXygSl36NMKgM/ZKvUsEAe6mF0Kb9pZRB7b/aV+ajkCQ rkQCe0KKSF6+D3wu3SmMe0NTc3/GkgxZN0lTnqUaB5PSRqwvVwurXugnAKr7arhj JSu9/QSeOxNI5ytDF1Nf9/RN0DT+L1w0vun083DupyJkG1hrjzm9kI0lACQTr/QX TxAWXGjiTsUOeM4pfNzqaJE4fNUc0TIc41jgWMx9qXzbKjhijgKEPtmyDMz93GVY hFXyRAMsWUOsQGP5tiLFYG0PkNsmCDIwca+yg47EicBQGTpEsGLYUBRvIILYNBKI ULl0yMLZWekl1rzthDdB =35xQ -----END PGP SIGNATURE----- Merge tag 'powerpc-4.8-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull one more powerpc fix from Michael Ellerman: "powernv/pci: Fix m64 checks for SR-IOV and window alignment from Russell Currey" * tag 'powerpc-4.8-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/powernv/pci: Fix m64 checks for SR-IOV and window alignment
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@ -124,6 +124,13 @@ static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
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r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
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r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
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}
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}
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static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
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{
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unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
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return (resource_flags & flags) == flags;
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}
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static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
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static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
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{
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{
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phb->ioda.pe_array[pe_no].phb = phb;
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phb->ioda.pe_array[pe_no].phb = phb;
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@ -2871,7 +2878,7 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
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res = &pdev->resource[i + PCI_IOV_RESOURCES];
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res = &pdev->resource[i + PCI_IOV_RESOURCES];
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if (!res->flags || res->parent)
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if (!res->flags || res->parent)
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continue;
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continue;
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if (!pnv_pci_is_m64(phb, res)) {
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if (!pnv_pci_is_m64_flags(res->flags)) {
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dev_warn(&pdev->dev, "Don't support SR-IOV with"
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dev_warn(&pdev->dev, "Don't support SR-IOV with"
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" non M64 VF BAR%d: %pR. \n",
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" non M64 VF BAR%d: %pR. \n",
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i, res);
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i, res);
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@ -3096,7 +3103,7 @@ static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
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* alignment for any 64-bit resource, PCIe doesn't care and
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* alignment for any 64-bit resource, PCIe doesn't care and
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* bridges only do 64-bit prefetchable anyway.
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* bridges only do 64-bit prefetchable anyway.
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*/
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*/
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if (phb->ioda.m64_segsize && (type & IORESOURCE_MEM_64))
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if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
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return phb->ioda.m64_segsize;
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return phb->ioda.m64_segsize;
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if (type & IORESOURCE_MEM)
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if (type & IORESOURCE_MEM)
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return phb->ioda.m32_segsize;
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return phb->ioda.m32_segsize;
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