drm/mediatek: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo effor. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
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@ -39,6 +39,7 @@
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#define DSI_CON_CTRL 0x10
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#define DSI_RESET BIT(0)
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#define DSI_EN BIT(1)
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#define DPHY_RESET BIT(2)
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#define DSI_MODE_CTRL 0x14
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#define MODE (3)
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@ -282,6 +283,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
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mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
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}
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static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
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{
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mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
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mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
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}
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static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
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{
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mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
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@ -652,6 +659,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
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mtk_dsi_phy_timconfig(dsi);
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mtk_dsi_rxtx_control(dsi);
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usleep_range(30, 100);
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mtk_dsi_reset_dphy(dsi);
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mtk_dsi_ps_control_vact(dsi);
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mtk_dsi_set_vm_cmd(dsi);
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mtk_dsi_config_vdo_timing(dsi);
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