ARM: i.MX5: Add nand oftree support
This adds snippets to the i.MX51/53 devicetrees for the nand flash controller. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -259,6 +259,13 @@
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status = "disabled";
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};
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nand@83fdb000 {
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compatible = "fsl,imx51-nand";
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reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
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interrupts = <8>;
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status = "disabled";
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};
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ssi3: ssi@83fe8000 {
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x83fe8000 0x4000>;
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@ -314,6 +314,13 @@
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status = "disabled";
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};
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nand@63fdb000 {
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compatible = "fsl,imx53-nand";
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reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
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interrupts = <8>;
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status = "disabled";
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};
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ssi3: ssi@63fe8000 {
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compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
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reg = <0x63fe8000 0x4000>;
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@ -357,6 +357,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
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clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
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clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
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clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
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/* set the usboh3 parent to pll2_sw */
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clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
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@ -446,6 +447,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
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clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
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clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
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clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
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/* set SDHC root clock to 200MHZ*/
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clk_set_rate(clk[esdhc_a_podf], 200000000);
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