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drm/amdgpu: correct mmBIF_SDMA4_DOORBELL_RANGE address for aldebaran

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On aldebaran, mmBIF_SDMA4_DOORBELL_RANGE isn't right next to
mmBIF_SDMA3_DOORBELL_RANGE.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma 2019-11-18 18:14:36 +08:00 committed by Alex Deucher
parent b61a273e5d
commit 759eb38ed1
1 changed files with 14 additions and 4 deletions
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18
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
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@ -92,10 +92,10 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
{
u32 reg, doorbell_range;
if (instance < 2)
if (instance < 2) {
reg = instance +
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
else
} else {
/*
* These registers address of SDMA2~7 is not consecutive
* from SDMA0~1. Need plus 4 dwords offset.
@ -103,9 +103,19 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
* BIF_SDMA0_DOORBELL_RANGE: 0x3bc0
* BIF_SDMA1_DOORBELL_RANGE: 0x3bc4
* BIF_SDMA2_DOORBELL_RANGE: 0x3bd8
+ * BIF_SDMA4_DOORBELL_RANGE:
+ * ARCTURUS: 0x3be0
+ * ALDEBARAN: 0x3be4
*/
reg = instance + 0x4 +
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
reg = instance + 0x4 + 0x1 +
SOC15_REG_OFFSET(NBIO, 0,
mmBIF_SDMA0_DOORBELL_RANGE);
else
reg = instance + 0x4 +
SOC15_REG_OFFSET(NBIO, 0,
mmBIF_SDMA0_DOORBELL_RANGE);
}
doorbell_range = RREG32(reg);