ARM: 5963/1: ux500: add support for u8500 v1 revision
Add cpu_is_u8500{ed/v1}() functions to determine the variant based on the CPU id, add the changed peripheral addresses, and fixup the MTU address. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -40,15 +40,27 @@ static struct map_desc u8500_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
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};
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static struct map_desc u8500ed_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
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};
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static struct map_desc u8500v1_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE_V1, SZ_4K),
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};
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void __init u8500_map_io(void)
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{
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iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
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if (cpu_is_u8500ed())
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iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
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else
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iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
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}
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void __init u8500_init_irq(void)
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@ -75,7 +87,10 @@ static void __init u8500_timer_init(void)
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twd_base = __io_address(U8500_TWD_BASE);
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#endif
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/* Setup the MTU base */
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mtu_base = __io_address(U8500_MTU0_BASE);
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if (cpu_is_u8500ed())
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mtu_base = __io_address(U8500_MTU0_BASE_ED);
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else
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mtu_base = __io_address(U8500_MTU0_BASE_V1);
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nmdk_timer_init();
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}
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@ -56,16 +56,19 @@
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#define U8500_TWD_SIZE 0x100
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/* per7 base addressess */
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#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
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#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
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#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
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#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
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#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
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#define U8500_CR_BASE_ED (U8500_PER7_BASE + 0x8000)
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#define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000)
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#define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000)
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#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE + 0xc000)
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#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE + 0xf000)
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/* per6 base addressess */
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#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
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#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
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#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
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#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
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#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
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#define U8500_CR_BASE_V1 (U8500_PER6_BASE + 0x8000)
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#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
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#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
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#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
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@ -128,4 +131,20 @@
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/* ST-Ericsson modified pl022 id */
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#define SSP_PER_ID 0x01080022
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#ifndef __ASSEMBLY__
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#include <asm/cputype.h>
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static inline bool cpu_is_u8500ed(void)
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{
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return (read_cpuid_id() & 15) == 0;
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}
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static inline bool cpu_is_u8500v1(void)
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{
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return (read_cpuid_id() & 15) == 1;
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}
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#endif
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#endif /* __MACH_HARDWARE_H */
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