drm/amdgpu: refine amdgpu ras event id core code
v1: - use unified event id to manage ras events - add a new function amdgpu_ras_query_error_status_with_event() to accept event type as parameter. v2: add a warn log to show the location of function failure when calling amdgpu_ras_mark_event(). (Tao Zhou) v3: change RAS_EVENT_TYPE_ISR to RAS_EVENT_TYPE_FATAL. v4: rename amdgpu_ras_get_recovery_event() to amdgpu_ras_get_fatal_error_event(). Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yang Wang
Alex Deucher
parent
e33697141b
commit
75ac6a2506
@ -119,7 +119,7 @@ static struct aca_regs_dump {
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static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,
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struct ras_query_context *qctx)
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{
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u64 event_id = qctx ? qctx->event_id : 0ULL;
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u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;
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int i;
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RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");
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@ -274,7 +274,7 @@ int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
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static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry,
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struct ras_query_context *qctx)
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{
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u64 event_id = qctx->event_id;
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u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;
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RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");
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RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n",
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@ -543,7 +543,7 @@ static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
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amdgpu_mca_bank_set_init(&mca_set);
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qctx.event_id = 0ULL;
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qctx.evid.event_id = RAS_EVENT_INVALID_ID;
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ret = amdgpu_mca_smu_get_mca_set(adev, type, &mca_set, &qctx);
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if (ret)
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goto err_free_mca_set;
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@ -1055,7 +1055,7 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
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struct amdgpu_smuio_mcm_config_info *mcm_info;
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struct ras_err_node *err_node;
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struct ras_err_info *err_info;
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u64 event_id = qctx->event_id;
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u64 event_id = qctx->evid.event_id;
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if (is_ue) {
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for_each_ras_error(err_node, err_data) {
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@ -1140,7 +1140,7 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
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{
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struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
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const char *blk_name = get_ras_block_str(&query_if->head);
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u64 event_id = qctx->event_id;
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u64 event_id = qctx->evid.event_id;
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if (err_data->ce_count) {
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if (err_data_has_source_info(err_data)) {
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@ -1366,7 +1366,9 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
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}
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/* query/inject/cure begin */
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int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
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static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev,
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struct ras_query_if *info,
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enum ras_event_type type)
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{
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
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struct ras_err_data err_data;
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@ -1385,8 +1387,8 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_i
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return -EINVAL;
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memset(&qctx, 0, sizeof(qctx));
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qctx.event_id = amdgpu_ras_acquire_event_id(adev, amdgpu_ras_intr_triggered() ?
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RAS_EVENT_TYPE_ISR : RAS_EVENT_TYPE_INVALID);
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qctx.evid.type = type;
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qctx.evid.event_id = amdgpu_ras_acquire_event_id(adev, type);
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if (!down_read_trylock(&adev->reset_domain->sem)) {
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ret = -EIO;
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@ -1415,6 +1417,11 @@ out_fini_err_data:
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return ret;
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}
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int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
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{
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return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID);
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}
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int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
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enum amdgpu_ras_block block)
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{
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@ -2305,7 +2312,7 @@ static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
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/* ih end */
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/* traversal all IPs except NBIO to query error counter */
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static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
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static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev, enum ras_event_type type)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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@ -2338,7 +2345,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
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IP_VERSION(13, 0, 2)))
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continue;
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amdgpu_ras_query_error_status(adev, &info);
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amdgpu_ras_query_error_status_with_event(adev, &info, type);
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if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
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IP_VERSION(11, 0, 2) &&
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@ -2477,6 +2484,14 @@ bool amdgpu_ras_in_recovery(struct amdgpu_device *adev)
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return false;
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}
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static enum ras_event_type amdgpu_ras_get_fatal_error_event(struct amdgpu_device *adev)
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{
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if (amdgpu_ras_intr_triggered())
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return RAS_EVENT_TYPE_FATAL;
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else
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return RAS_EVENT_TYPE_INVALID;
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}
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static void amdgpu_ras_do_recovery(struct work_struct *work)
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{
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struct amdgpu_ras *ras =
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@ -2485,6 +2500,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
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struct amdgpu_device *adev = ras->adev;
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struct list_head device_list, *device_list_handle = NULL;
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struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
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enum ras_event_type type;
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if (hive) {
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atomic_set(&hive->ras_recovery, 1);
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@ -2512,10 +2528,11 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
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device_list_handle = &device_list;
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}
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type = amdgpu_ras_get_fatal_error_event(adev);
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list_for_each_entry(remote_adev,
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device_list_handle, gmc.xgmi.head) {
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amdgpu_ras_query_err_status(remote_adev);
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amdgpu_ras_log_on_err_counter(remote_adev);
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amdgpu_ras_log_on_err_counter(remote_adev, type);
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}
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}
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@ -3406,8 +3423,11 @@ static void ras_event_mgr_init(struct ras_event_manager *mgr)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mgr->seqnos); i++)
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atomic64_set(&mgr->seqnos[i], 0);
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memset(mgr, 0, sizeof(*mgr));
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atomic64_set(&mgr->seqno, 0);
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for (i = 0; i < ARRAY_SIZE(mgr->last_seqno); i++)
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mgr->last_seqno[i] = RAS_EVENT_INVALID_ID;
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}
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static void amdgpu_ras_event_mgr_init(struct amdgpu_device *adev)
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@ -3907,23 +3927,63 @@ void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)
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atomic_set(&ras->fed, !!status);
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}
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bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id)
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static struct ras_event_manager *__get_ras_event_mgr(struct amdgpu_device *adev)
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{
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return !(id & BIT_ULL(63));
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struct amdgpu_ras *ras;
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ras = amdgpu_ras_get_context(adev);
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if (!ras)
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return NULL;
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return ras->event_mgr;
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}
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int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
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const void *caller)
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{
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struct ras_event_manager *event_mgr;
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int ret = 0;
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if (type >= RAS_EVENT_TYPE_COUNT) {
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ret = -EINVAL;
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goto out;
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}
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event_mgr = __get_ras_event_mgr(adev);
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if (!event_mgr) {
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ret = -EINVAL;
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goto out;
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}
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event_mgr->last_seqno[type] = atomic64_inc_return(&event_mgr->seqno);
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out:
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if (ret && caller)
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dev_warn(adev->dev, "failed mark ras event (%d) in %ps, ret:%d\n",
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(int)type, caller, ret);
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return ret;
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}
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u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type)
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{
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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struct ras_event_manager *event_mgr;
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u64 id;
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if (type >= RAS_EVENT_TYPE_COUNT)
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return RAS_EVENT_INVALID_ID;
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switch (type) {
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case RAS_EVENT_TYPE_ISR:
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id = (u64)atomic64_read(&ras->event_mgr->seqnos[type]);
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case RAS_EVENT_TYPE_FATAL:
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event_mgr = __get_ras_event_mgr(adev);
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if (!event_mgr)
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return RAS_EVENT_INVALID_ID;
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id = event_mgr->last_seqno[type];
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break;
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case RAS_EVENT_TYPE_INVALID:
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default:
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id = BIT_ULL(63) | 0ULL;
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id = RAS_EVENT_INVALID_ID;
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break;
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}
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@ -3934,7 +3994,13 @@ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
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{
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if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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u64 event_id = (u64)atomic64_inc_return(&ras->event_mgr->seqnos[RAS_EVENT_TYPE_ISR]);
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enum ras_event_type type = RAS_EVENT_TYPE_FATAL;
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u64 event_id;
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if (amdgpu_ras_mark_ras_event(adev, type))
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return;
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event_id = amdgpu_ras_acquire_event_id(adev, type);
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RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error"
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"(ERREVENT_ATHUB_INTERRUPT) detected!\n");
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@ -4668,7 +4734,7 @@ void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
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vaf.fmt = fmt;
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vaf.va = &args;
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if (amdgpu_ras_event_id_is_valid(adev, event_id))
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if (RAS_EVENT_ID_IS_VALID(event_id))
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dev_printk(KERN_INFO, adev->dev, "{%llu}%pV", event_id, &vaf);
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else
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dev_printk(KERN_INFO, adev->dev, "%pV", &vaf);
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@ -68,9 +68,15 @@ struct amdgpu_iv_entry;
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/* The high three bits indicates socketid */
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#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
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#define RAS_EVENT_INVALID_ID (BIT_ULL(63))
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#define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63)))
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#define RAS_EVENT_LOG(adev, id, fmt, ...) \
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amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__)
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#define amdgpu_ras_mark_ras_event(adev, type) \
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(amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0)))
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enum amdgpu_ras_block {
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AMDGPU_RAS_BLOCK__UMC = 0,
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AMDGPU_RAS_BLOCK__SDMA,
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@ -427,18 +433,23 @@ struct umc_ecc_info {
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};
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enum ras_event_type {
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RAS_EVENT_TYPE_INVALID = -1,
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RAS_EVENT_TYPE_ISR = 0,
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RAS_EVENT_TYPE_INVALID = 0,
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RAS_EVENT_TYPE_FATAL,
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RAS_EVENT_TYPE_COUNT,
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};
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struct ras_event_manager {
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atomic64_t seqnos[RAS_EVENT_TYPE_COUNT];
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atomic64_t seqno;
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u64 last_seqno[RAS_EVENT_TYPE_COUNT];
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};
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struct ras_event_id {
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enum ras_event_type type;
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u64 event_id;
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};
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struct ras_query_context {
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enum ras_event_type type;
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u64 event_id;
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struct ras_event_id evid;
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};
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typedef int (*pasid_notify)(struct amdgpu_device *adev,
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@ -947,8 +958,9 @@ void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info,
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void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
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bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
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bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id);
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u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
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int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
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const void *caller);
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int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
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