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clk: samsung: fsd: Add cmu_mfc block clock information

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Adds cmu_mfc clock related code, these clocks are
required for MFC IP.

Cc: linux-fsd@tesla.com
Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-10-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Alim Akhtar 2022-01-24 19:46:37 +05:30 committed by Krzysztof Kozlowski
parent ca0fdfd131
commit 75c50afaa0
1 changed files with 121 additions and 0 deletions
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121
drivers/clk/samsung/clk-fsd.c
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@ -1427,6 +1427,124 @@ static void __init fsd_clk_imem_init(struct device_node *np)
CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
/* Register Offset definitions for CMU_MFC (0x12810000) */
#define PLL_LOCKTIME_PLL_MFC 0x0
#define PLL_CON0_PLL_MFC 0x100
#define MUX_MFC_BUSD 0x1000
#define MUX_MFC_BUSP 0x1008
#define DIV_MFC_BUSD_DIV4 0x1800
#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
#define GAT_MFC_BUSD_DIV4_GATE 0x2044
#define GAT_MFC_BUSD_GATE 0x2048
static const unsigned long mfc_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_MFC,
PLL_CON0_PLL_MFC,
MUX_MFC_BUSD,
MUX_MFC_BUSP,
DIV_MFC_BUSD_DIV4,
GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
GAT_MFC_MFC_IPCLKPORT_ACLK,
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
GAT_MFC_BUSD_DIV4_GATE,
GAT_MFC_BUSD_GATE,
};
static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
};
static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
};
PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
};
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
};
static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.pll_clks = mfc_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mfc_pll_clks),
.mux_clks = mfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
.div_clks = mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = MFC_NR_CLK,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@ -1455,6 +1573,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-fsys1",
.data = &fsys1_cmu_info,
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
}, {
},
};