drm/amdgpu: enable ras on gfx9 (v2)
Register ecc interrupts and ecc interrupt handler on gfx9. Add ras support on gfx9 v2: squash in warning fix Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Feifei Xu
Alex Deucher
parent
8cf12507d3
commit
760a1d5534
@ -258,6 +258,9 @@ struct amdgpu_gfx {
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/* pipe reservation */
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struct mutex pipe_reserve_mutex;
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DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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/*ras */
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struct ras_common_if *ras_if;
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};
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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@ -40,6 +40,8 @@
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#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
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#include "amdgpu_ras.h"
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#define GFX9_NUM_GFX_RINGS 1
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#define GFX9_MEC_HPD_SIZE 4096
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#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
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@ -1638,6 +1640,18 @@ static int gfx_v9_0_sw_init(void *handle)
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if (r)
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return r;
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/* ECC error */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR,
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&adev->gfx.cp_ecc_error_irq);
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if (r)
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return r;
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/* FUE error */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR,
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&adev->gfx.cp_ecc_error_irq);
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if (r)
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return r;
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adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
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gfx_v9_0_scratch_init(adev);
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@ -1730,6 +1744,20 @@ static int gfx_v9_0_sw_fini(void *handle)
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int i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
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adev->gfx.ras_if) {
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struct ras_common_if *ras_if = adev->gfx.ras_if;
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struct ras_ih_if ih_info = {
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.head = *ras_if,
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};
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amdgpu_ras_debugfs_remove(adev, ras_if);
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amdgpu_ras_sysfs_remove(adev, ras_if);
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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amdgpu_ras_feature_enable(adev, ras_if, 0);
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kfree(ras_if);
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}
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amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
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amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
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amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
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@ -3304,6 +3332,7 @@ static int gfx_v9_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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@ -3493,6 +3522,77 @@ static int gfx_v9_0_early_init(void *handle)
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return 0;
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}
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static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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static int gfx_v9_0_ecc_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ras_common_if **ras_if = &adev->gfx.ras_if;
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struct ras_ih_if ih_info = {
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.cb = gfx_v9_0_process_ras_data_cb,
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "gfx_err_count",
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.debugfs_name = "gfx_err_inject",
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};
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struct ras_common_if ras_block = {
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.block = AMDGPU_RAS_BLOCK__GFX,
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.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
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.sub_block_index = 0,
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.name = "gfx",
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};
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int r;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
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amdgpu_ras_feature_enable(adev, &ras_block, 0);
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return 0;
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}
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*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
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if (!*ras_if)
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return -ENOMEM;
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**ras_if = ras_block;
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r = amdgpu_ras_feature_enable(adev, *ras_if, 1);
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if (r)
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goto feature;
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ih_info.head = **ras_if;
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fs_info.head = **ras_if;
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r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
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if (r)
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goto interrupt;
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r = amdgpu_ras_debugfs_create(adev, &fs_info);
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if (r)
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goto debugfs;
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r = amdgpu_ras_sysfs_create(adev, &fs_info);
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if (r)
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goto sysfs;
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r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
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if (r)
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goto irq;
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return 0;
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irq:
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amdgpu_ras_sysfs_remove(adev, *ras_if);
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sysfs:
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amdgpu_ras_debugfs_remove(adev, *ras_if);
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debugfs:
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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interrupt:
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amdgpu_ras_feature_enable(adev, *ras_if, 0);
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feature:
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kfree(*ras_if);
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*ras_if = NULL;
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return -EINVAL;
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}
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static int gfx_v9_0_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -3506,6 +3606,10 @@ static int gfx_v9_0_late_init(void *handle)
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if (r)
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return r;
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r = gfx_v9_0_ecc_late_init(handle);
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if (r)
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return r;
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return 0;
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}
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@ -4542,6 +4646,45 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
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return 0;
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}
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#define ENABLE_ECC_ON_ME_PIPE(me, pipe) \
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WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
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CP_ECC_ERROR_INT_ENABLE, 1)
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#define DISABLE_ECC_ON_ME_PIPE(me, pipe) \
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WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
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CP_ECC_ERROR_INT_ENABLE, 0)
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static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
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CP_ECC_ERROR_INT_ENABLE, 0);
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DISABLE_ECC_ON_ME_PIPE(1, 0);
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DISABLE_ECC_ON_ME_PIPE(1, 1);
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DISABLE_ECC_ON_ME_PIPE(1, 2);
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DISABLE_ECC_ON_ME_PIPE(1, 3);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
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CP_ECC_ERROR_INT_ENABLE, 1);
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ENABLE_ECC_ON_ME_PIPE(1, 0);
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ENABLE_ECC_ON_ME_PIPE(1, 1);
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ENABLE_ECC_ON_ME_PIPE(1, 2);
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ENABLE_ECC_ON_ME_PIPE(1, 3);
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break;
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default:
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break;
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}
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return 0;
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}
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static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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@ -4658,6 +4801,27 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
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return 0;
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}
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static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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/* TODO ue will trigger an interrupt. */
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amdgpu_ras_reset_gpu(adev, 0);
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return AMDGPU_RAS_UE;
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}
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static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct ras_dispatch_if ih_data = {
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.head = *adev->gfx.ras_if,
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.entry = entry,
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};
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DRM_ERROR("CP ECC ERROR IRQ\n");
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amdgpu_ras_interrupt_dispatch(adev, &ih_data);
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return 0;
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}
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static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
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.name = "gfx_v9_0",
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.early_init = gfx_v9_0_early_init,
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@ -4819,6 +4983,12 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
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.process = gfx_v9_0_priv_inst_irq,
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};
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static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
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.set = gfx_v9_0_set_cp_ecc_error_state,
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.process = gfx_v9_0_cp_ecc_error_irq,
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};
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static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
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@ -4829,6 +4999,9 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
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adev->gfx.priv_inst_irq.num_types = 1;
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adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
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adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
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adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
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}
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static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
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