crypto: hisilicon/qm - update reset flow
This patch updates the reset flow based on PF/VF communications. VFs will be stopped after receiving reset message from PF, and wait for reset finish to restart VFs. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Weili Qian
Herbert Xu
parent
3cd53a27c2
commit
760fe22cf5
@ -201,7 +201,10 @@
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#define QM_WAIT_DST_ACK 10
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#define QM_MAX_PF_WAIT_COUNT 10
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#define QM_MAX_VF_WAIT_COUNT 40
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#define QM_VF_RESET_WAIT_US 20000
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#define QM_VF_RESET_WAIT_CNT 3000
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#define QM_VF_RESET_WAIT_TIMEOUT_US \
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(QM_VF_RESET_WAIT_US * QM_VF_RESET_WAIT_CNT)
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#define QM_DFX_MB_CNT_VF 0x104010
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#define QM_DFX_DB_CNT_VF 0x104020
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@ -285,6 +288,16 @@ enum acc_err_result {
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ACC_ERR_RECOVERED,
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};
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enum qm_mb_cmd {
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QM_PF_FLR_PREPARE = 0x01,
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QM_PF_SRST_PREPARE,
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QM_PF_RESET_DONE,
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QM_VF_PREPARE_DONE,
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QM_VF_PREPARE_FAIL,
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QM_VF_START_DONE,
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QM_VF_START_FAIL,
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};
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struct qm_cqe {
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__le32 rsvd0;
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__le16 cmd_id;
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@ -1890,9 +1903,74 @@ static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)
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writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
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}
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static void qm_handle_vf_msg(struct hisi_qm *qm, u32 vf_id)
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{
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struct device *dev = &qm->pdev->dev;
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u32 cmd;
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u64 msg;
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int ret;
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ret = qm_get_mb_cmd(qm, &msg, vf_id);
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if (ret) {
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dev_err(dev, "failed to get msg from VF(%u)!\n", vf_id);
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return;
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}
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cmd = msg & QM_MB_CMD_DATA_MASK;
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switch (cmd) {
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case QM_VF_PREPARE_FAIL:
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dev_err(dev, "failed to stop VF(%u)!\n", vf_id);
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break;
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case QM_VF_START_FAIL:
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dev_err(dev, "failed to start VF(%u)!\n", vf_id);
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break;
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case QM_VF_PREPARE_DONE:
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case QM_VF_START_DONE:
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break;
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default:
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dev_err(dev, "unsupported cmd %u sent by VF(%u)!\n", cmd, vf_id);
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break;
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}
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}
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static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)
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{
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return 0;
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struct device *dev = &qm->pdev->dev;
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u32 vfs_num = qm->vfs_num;
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int cnt = 0;
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int ret = 0;
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u64 val;
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u32 i;
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if (!qm->vfs_num || qm->ver < QM_HW_V3)
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return 0;
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while (true) {
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val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
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/* All VFs send command to PF, break */
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if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))
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break;
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if (++cnt > QM_MAX_PF_WAIT_COUNT) {
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ret = -EBUSY;
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break;
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}
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msleep(QM_WAIT_DST_ACK);
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}
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/* PF check VFs msg */
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for (i = 1; i <= vfs_num; i++) {
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if (val & BIT(i))
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qm_handle_vf_msg(qm, i);
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else
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dev_err(dev, "VF(%u) not ping PF!\n", i);
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}
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/* PF clear interrupt to ack VFs */
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qm_clear_cmd_interrupt(qm, val);
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return ret;
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}
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static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)
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@ -4038,7 +4116,8 @@ stop_fail:
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return ret;
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}
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static int qm_try_stop_vfs(struct hisi_qm *qm, enum qm_stop_reason stop_reason)
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static int qm_try_stop_vfs(struct hisi_qm *qm, u64 cmd,
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enum qm_stop_reason stop_reason)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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@ -4046,9 +4125,16 @@ static int qm_try_stop_vfs(struct hisi_qm *qm, enum qm_stop_reason stop_reason)
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if (!qm->vfs_num)
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return 0;
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ret = qm_vf_reset_prepare(qm, stop_reason);
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if (ret)
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pci_err(pdev, "failed to prepare reset, ret = %d.\n", ret);
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/* Kunpeng930 supports to notify VFs to stop before PF reset */
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if (qm->ops->ping_all_vfs) {
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ret = qm->ops->ping_all_vfs(qm, cmd);
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if (ret)
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pci_err(pdev, "failed to send cmd to all VFs before PF reset!\n");
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} else {
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ret = qm_vf_reset_prepare(qm, stop_reason);
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if (ret)
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pci_err(pdev, "failed to prepare reset, ret = %d.\n", ret);
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}
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return ret;
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}
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@ -4072,7 +4158,14 @@ static int qm_reset_prepare_ready(struct hisi_qm *qm)
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struct pci_dev *pdev = qm->pdev;
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struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
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return qm_wait_reset_finish(pf_qm);
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/*
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* PF and VF on host doesnot support resetting at the
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* same time on Kunpeng920.
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*/
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if (qm->ver < QM_HW_V3)
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return qm_wait_reset_finish(pf_qm);
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return qm_wait_reset_finish(qm);
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}
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static void qm_reset_bit_clear(struct hisi_qm *qm)
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@ -4080,7 +4173,10 @@ static void qm_reset_bit_clear(struct hisi_qm *qm)
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struct pci_dev *pdev = qm->pdev;
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struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
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clear_bit(QM_RESETTING, &pf_qm->misc_ctl);
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if (qm->ver < QM_HW_V3)
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clear_bit(QM_RESETTING, &pf_qm->misc_ctl);
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clear_bit(QM_RESETTING, &qm->misc_ctl);
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}
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static int qm_controller_reset_prepare(struct hisi_qm *qm)
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@ -4094,7 +4190,11 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm)
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return ret;
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}
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ret = qm_try_stop_vfs(qm, QM_SOFT_RESET);
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/* PF obtains the information of VF by querying the register. */
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qm_cmd_uninit(qm);
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/* Whether VFs stop successfully, soft reset will continue. */
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ret = qm_try_stop_vfs(qm, QM_PF_SRST_PREPARE, QM_SOFT_RESET);
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if (ret)
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pci_err(pdev, "failed to stop vfs by pf in soft reset.\n");
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@ -4243,7 +4343,7 @@ restart_fail:
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return ret;
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}
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static int qm_try_start_vfs(struct hisi_qm *qm)
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static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_mb_cmd cmd)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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@ -4257,9 +4357,16 @@ static int qm_try_start_vfs(struct hisi_qm *qm)
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return ret;
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}
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ret = qm_vf_reset_done(qm);
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if (ret)
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pci_warn(pdev, "failed to start vfs, ret = %d.\n", ret);
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/* Kunpeng930 supports to notify VFs to start after PF reset. */
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if (qm->ops->ping_all_vfs) {
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ret = qm->ops->ping_all_vfs(qm, cmd);
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if (ret)
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pci_warn(pdev, "failed to send cmd to all VFs after PF reset!\n");
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} else {
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ret = qm_vf_reset_done(qm);
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if (ret)
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pci_warn(pdev, "failed to start vfs, ret = %d.\n", ret);
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}
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return ret;
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}
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@ -4363,7 +4470,7 @@ static int qm_controller_reset_done(struct hisi_qm *qm)
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return ret;
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}
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ret = qm_try_start_vfs(qm);
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ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
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if (ret)
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pci_err(pdev, "failed to start vfs by pf in soft reset.\n");
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@ -4371,6 +4478,7 @@ static int qm_controller_reset_done(struct hisi_qm *qm)
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if (ret)
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pci_err(pdev, "failed to start by vfs in soft reset!\n");
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qm_cmd_init(qm);
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qm_restart_done(qm);
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qm_reset_bit_clear(qm);
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@ -4462,7 +4570,11 @@ void hisi_qm_reset_prepare(struct pci_dev *pdev)
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return;
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}
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ret = qm_try_stop_vfs(qm, QM_SOFT_RESET);
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/* PF obtains the information of VF by querying the register. */
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if (qm->fun_type == QM_HW_PF)
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qm_cmd_uninit(qm);
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ret = qm_try_stop_vfs(qm, QM_PF_FLR_PREPARE, QM_FLR);
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if (ret)
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pci_err(pdev, "failed to stop vfs by pf in FLR.\n");
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@ -4517,7 +4629,7 @@ void hisi_qm_reset_done(struct pci_dev *pdev)
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goto flr_done;
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}
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ret = qm_try_start_vfs(qm);
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ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
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if (ret)
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pci_err(pdev, "failed to start vfs by pf in FLR.\n");
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@ -4526,6 +4638,9 @@ void hisi_qm_reset_done(struct pci_dev *pdev)
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pci_err(pdev, "failed to start by vfs in FLR!\n");
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flr_done:
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if (qm->fun_type == QM_HW_PF)
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qm_cmd_init(qm);
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if (qm_flr_reset_complete(pdev))
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pci_info(pdev, "FLR reset complete\n");
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@ -4621,12 +4736,128 @@ static void hisi_qm_controller_reset(struct work_struct *rst_work)
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}
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static void qm_pf_reset_vf_prepare(struct hisi_qm *qm,
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enum qm_stop_reason stop_reason)
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{
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enum qm_mb_cmd cmd = QM_VF_PREPARE_DONE;
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struct pci_dev *pdev = qm->pdev;
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int ret;
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ret = qm_reset_prepare_ready(qm);
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if (ret) {
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dev_err(&pdev->dev, "reset prepare not ready!\n");
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atomic_set(&qm->status.flags, QM_STOP);
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cmd = QM_VF_PREPARE_FAIL;
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goto err_prepare;
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}
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ret = hisi_qm_stop(qm, stop_reason);
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if (ret) {
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dev_err(&pdev->dev, "failed to stop QM, ret = %d.\n", ret);
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atomic_set(&qm->status.flags, QM_STOP);
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cmd = QM_VF_PREPARE_FAIL;
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goto err_prepare;
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}
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err_prepare:
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pci_save_state(pdev);
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ret = qm->ops->ping_pf(qm, cmd);
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if (ret)
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dev_warn(&pdev->dev, "PF responds timeout in reset prepare!\n");
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}
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static void qm_pf_reset_vf_done(struct hisi_qm *qm)
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{
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enum qm_mb_cmd cmd = QM_VF_START_DONE;
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struct pci_dev *pdev = qm->pdev;
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int ret;
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pci_restore_state(pdev);
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ret = hisi_qm_start(qm);
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if (ret) {
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dev_err(&pdev->dev, "failed to start QM, ret = %d.\n", ret);
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cmd = QM_VF_START_FAIL;
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}
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ret = qm->ops->ping_pf(qm, cmd);
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if (ret)
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dev_warn(&pdev->dev, "PF responds timeout in reset done!\n");
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qm_reset_bit_clear(qm);
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}
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static int qm_wait_pf_reset_finish(struct hisi_qm *qm)
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{
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struct device *dev = &qm->pdev->dev;
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u32 val, cmd;
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u64 msg;
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int ret;
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/* Wait for reset to finish */
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ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
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val == BIT(0), QM_VF_RESET_WAIT_US,
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QM_VF_RESET_WAIT_TIMEOUT_US);
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/* hardware completion status should be available by this time */
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if (ret) {
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dev_err(dev, "couldn't get reset done status from PF, timeout!\n");
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return -ETIMEDOUT;
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}
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/*
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* Whether message is got successfully,
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* VF needs to ack PF by clearing the interrupt.
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*/
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ret = qm_get_mb_cmd(qm, &msg, 0);
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qm_clear_cmd_interrupt(qm, 0);
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if (ret) {
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dev_err(dev, "failed to get msg from PF in reset done!\n");
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return ret;
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}
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cmd = msg & QM_MB_CMD_DATA_MASK;
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if (cmd != QM_PF_RESET_DONE) {
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dev_err(dev, "the cmd(%u) is not reset done!\n", cmd);
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ret = -EINVAL;
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}
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return ret;
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}
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static void qm_pf_reset_vf_process(struct hisi_qm *qm,
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enum qm_stop_reason stop_reason)
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{
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struct device *dev = &qm->pdev->dev;
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int ret;
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dev_info(dev, "device reset start...\n");
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/* The message is obtained by querying the register during resetting */
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qm_cmd_uninit(qm);
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qm_pf_reset_vf_prepare(qm, stop_reason);
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ret = qm_wait_pf_reset_finish(qm);
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if (ret)
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goto err_get_status;
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qm_pf_reset_vf_done(qm);
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qm_cmd_init(qm);
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dev_info(dev, "device reset done.\n");
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return;
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err_get_status:
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qm_cmd_init(qm);
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qm_reset_bit_clear(qm);
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}
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static void qm_cmd_process(struct work_struct *cmd_process)
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{
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struct hisi_qm *qm = container_of(cmd_process,
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struct hisi_qm, cmd_process);
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struct device *dev = &qm->pdev->dev;
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u64 msg;
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u32 cmd;
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int ret;
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/*
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@ -4635,9 +4866,23 @@ static void qm_cmd_process(struct work_struct *cmd_process)
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*/
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ret = qm_get_mb_cmd(qm, &msg, 0);
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qm_clear_cmd_interrupt(qm, 0);
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if (ret)
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if (ret) {
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dev_err(dev, "failed to get msg from source!\n");
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return;
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}
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cmd = msg & QM_MB_CMD_DATA_MASK;
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switch (cmd) {
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case QM_PF_FLR_PREPARE:
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qm_pf_reset_vf_process(qm, QM_FLR);
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break;
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case QM_PF_SRST_PREPARE:
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qm_pf_reset_vf_process(qm, QM_SOFT_RESET);
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break;
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default:
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dev_err(dev, "unsupported cmd %u sent by PF!\n", cmd);
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break;
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}
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}
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/**
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