MIPS: introduce cpu_coherent_mask
Add a mask of CPUs which are currently known to be operating coherently. This is setup initially to be all present CPUs, but in a subsequent patch CPUs in a MIPS Coherent Processing System will be cleared in this mask as they enter non-coherent idle states. This will be used in order to determine when a CPU within a CPS system may need to be powered back up, but may also be used in future to optimise away wakeups for cache operations or TLB invalidations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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@ -46,6 +46,9 @@ extern int __cpu_logical_map[NR_CPUS];
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extern volatile cpumask_t cpu_callin_map;
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extern volatile cpumask_t cpu_callin_map;
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/* Mask of CPUs which are currently definitely operating coherently */
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extern cpumask_t cpu_coherent_mask;
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extern void asmlinkage smp_bootstrap(void);
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extern void asmlinkage smp_bootstrap(void);
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/*
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/*
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@ -66,6 +66,8 @@ EXPORT_SYMBOL(cpu_sibling_map);
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/* representing cpus for which sibling maps can be computed */
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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static cpumask_t cpu_sibling_setup_map;
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cpumask_t cpu_coherent_mask;
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static inline void set_cpu_sibling_map(int cpu)
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static inline void set_cpu_sibling_map(int cpu)
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{
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{
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int i;
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int i;
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@ -124,6 +126,7 @@ asmlinkage void start_secondary(void)
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cpu = smp_processor_id();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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cpu_set(cpu, cpu_coherent_mask);
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notify_cpu_starting(cpu);
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notify_cpu_starting(cpu);
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set_cpu_online(cpu, true);
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set_cpu_online(cpu, true);
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@ -186,6 +189,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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#ifndef CONFIG_HOTPLUG_CPU
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#ifndef CONFIG_HOTPLUG_CPU
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init_cpu_present(cpu_possible_mask);
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init_cpu_present(cpu_possible_mask);
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#endif
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#endif
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cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
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}
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}
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/* preload SMP state for boot cpu */
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/* preload SMP state for boot cpu */
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