Merge branch 'topic/omap' into for-linus
This commit is contained in:
Vinod Koul
commit
765630daa8
@ -8,6 +8,7 @@
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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@ -32,10 +33,12 @@ struct omap_dmadev {
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const struct omap_dma_reg *reg_map;
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struct omap_system_dma_plat_info *plat;
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bool legacy;
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bool ll123_supported;
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struct dma_pool *desc_pool;
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unsigned dma_requests;
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spinlock_t irq_lock;
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uint32_t irq_enable_mask;
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struct omap_chan *lch_map[OMAP_SDMA_CHANNELS];
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struct omap_chan **lch_map;
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};
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struct omap_chan {
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@ -55,16 +58,40 @@ struct omap_chan {
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unsigned sgidx;
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};
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#define DESC_NXT_SV_REFRESH (0x1 << 24)
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#define DESC_NXT_SV_REUSE (0x2 << 24)
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#define DESC_NXT_DV_REFRESH (0x1 << 26)
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#define DESC_NXT_DV_REUSE (0x2 << 26)
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#define DESC_NTYPE_TYPE2 (0x2 << 29)
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/* Type 2 descriptor with Source or Destination address update */
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struct omap_type2_desc {
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uint32_t next_desc;
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uint32_t en;
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uint32_t addr; /* src or dst */
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uint16_t fn;
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uint16_t cicr;
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int16_t cdei;
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int16_t csei;
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int32_t cdfi;
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int32_t csfi;
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} __packed;
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struct omap_sg {
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dma_addr_t addr;
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uint32_t en; /* number of elements (24-bit) */
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uint32_t fn; /* number of frames (16-bit) */
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int32_t fi; /* for double indexing */
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int16_t ei; /* for double indexing */
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/* Linked list */
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struct omap_type2_desc *t2_desc;
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dma_addr_t t2_desc_paddr;
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};
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struct omap_desc {
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struct virt_dma_desc vd;
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bool using_ll;
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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@ -81,6 +108,9 @@ struct omap_desc {
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};
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enum {
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CAPS_0_SUPPORT_LL123 = BIT(20), /* Linked List type1/2/3 */
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CAPS_0_SUPPORT_LL4 = BIT(21), /* Linked List type4 */
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CCR_FS = BIT(5),
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CCR_READ_PRIORITY = BIT(6),
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CCR_ENABLE = BIT(7),
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@ -151,6 +181,19 @@ enum {
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CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */
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CLNK_CTRL_ENABLE_LNK = BIT(15),
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CDP_DST_VALID_INC = 0 << 0,
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CDP_DST_VALID_RELOAD = 1 << 0,
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CDP_DST_VALID_REUSE = 2 << 0,
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CDP_SRC_VALID_INC = 0 << 2,
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CDP_SRC_VALID_RELOAD = 1 << 2,
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CDP_SRC_VALID_REUSE = 2 << 2,
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CDP_NTYPE_TYPE1 = 1 << 4,
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CDP_NTYPE_TYPE2 = 2 << 4,
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CDP_NTYPE_TYPE3 = 3 << 4,
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CDP_TMODE_NORMAL = 0 << 8,
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CDP_TMODE_LLIST = 1 << 8,
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CDP_FAST = BIT(10),
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};
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static const unsigned es_bytes[] = {
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@ -180,7 +223,64 @@ static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor
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static void omap_dma_desc_free(struct virt_dma_desc *vd)
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{
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kfree(container_of(vd, struct omap_desc, vd));
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struct omap_desc *d = to_omap_dma_desc(&vd->tx);
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if (d->using_ll) {
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struct omap_dmadev *od = to_omap_dma_dev(vd->tx.chan->device);
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int i;
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for (i = 0; i < d->sglen; i++) {
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if (d->sg[i].t2_desc)
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dma_pool_free(od->desc_pool, d->sg[i].t2_desc,
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d->sg[i].t2_desc_paddr);
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}
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}
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kfree(d);
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}
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static void omap_dma_fill_type2_desc(struct omap_desc *d, int idx,
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enum dma_transfer_direction dir, bool last)
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{
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struct omap_sg *sg = &d->sg[idx];
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struct omap_type2_desc *t2_desc = sg->t2_desc;
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if (idx)
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d->sg[idx - 1].t2_desc->next_desc = sg->t2_desc_paddr;
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if (last)
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t2_desc->next_desc = 0xfffffffc;
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t2_desc->en = sg->en;
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t2_desc->addr = sg->addr;
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t2_desc->fn = sg->fn & 0xffff;
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t2_desc->cicr = d->cicr;
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if (!last)
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t2_desc->cicr &= ~CICR_BLOCK_IE;
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switch (dir) {
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case DMA_DEV_TO_MEM:
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t2_desc->cdei = sg->ei;
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t2_desc->csei = d->ei;
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t2_desc->cdfi = sg->fi;
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t2_desc->csfi = d->fi;
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t2_desc->en |= DESC_NXT_DV_REFRESH;
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t2_desc->en |= DESC_NXT_SV_REUSE;
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break;
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case DMA_MEM_TO_DEV:
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t2_desc->cdei = d->ei;
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t2_desc->csei = sg->ei;
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t2_desc->cdfi = d->fi;
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t2_desc->csfi = sg->fi;
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t2_desc->en |= DESC_NXT_SV_REFRESH;
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t2_desc->en |= DESC_NXT_DV_REUSE;
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break;
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default:
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return;
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}
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t2_desc->en |= DESC_NTYPE_TYPE2;
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}
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static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
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@ -285,6 +385,7 @@ static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
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static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
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{
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struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
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uint16_t cicr = d->cicr;
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if (__dma_omap15xx(od->plat->dma_attr))
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omap_dma_chan_write(c, CPC, 0);
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@ -293,8 +394,27 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
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omap_dma_clear_csr(c);
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if (d->using_ll) {
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uint32_t cdp = CDP_TMODE_LLIST | CDP_NTYPE_TYPE2 | CDP_FAST;
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if (d->dir == DMA_DEV_TO_MEM)
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cdp |= (CDP_DST_VALID_RELOAD | CDP_SRC_VALID_REUSE);
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else
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cdp |= (CDP_DST_VALID_REUSE | CDP_SRC_VALID_RELOAD);
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omap_dma_chan_write(c, CDP, cdp);
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omap_dma_chan_write(c, CNDP, d->sg[0].t2_desc_paddr);
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omap_dma_chan_write(c, CCDN, 0);
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omap_dma_chan_write(c, CCFN, 0xffff);
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omap_dma_chan_write(c, CCEN, 0xffffff);
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cicr &= ~CICR_BLOCK_IE;
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} else if (od->ll123_supported) {
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omap_dma_chan_write(c, CDP, 0);
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}
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/* Enable interrupts */
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omap_dma_chan_write(c, CICR, d->cicr);
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omap_dma_chan_write(c, CICR, cicr);
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/* Enable channel */
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omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
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@ -365,10 +485,9 @@ static void omap_dma_stop(struct omap_chan *c)
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c->running = false;
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}
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static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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unsigned idx)
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static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d)
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{
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struct omap_sg *sg = d->sg + idx;
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struct omap_sg *sg = d->sg + c->sgidx;
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unsigned cxsa, cxei, cxfi;
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if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
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@ -388,6 +507,7 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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omap_dma_chan_write(c, CFN, sg->fn);
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omap_dma_start(c, d);
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c->sgidx++;
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}
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static void omap_dma_start_desc(struct omap_chan *c)
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@ -433,7 +553,7 @@ static void omap_dma_start_desc(struct omap_chan *c)
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omap_dma_chan_write(c, CSDP, d->csdp);
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omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
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omap_dma_start_sg(c, d, 0);
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omap_dma_start_sg(c, d);
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}
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static void omap_dma_callback(int ch, u16 status, void *data)
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@ -445,15 +565,13 @@ static void omap_dma_callback(int ch, u16 status, void *data)
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spin_lock_irqsave(&c->vc.lock, flags);
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d = c->desc;
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if (d) {
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if (!c->cyclic) {
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if (++c->sgidx < d->sglen) {
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omap_dma_start_sg(c, d, c->sgidx);
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} else {
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omap_dma_start_desc(c);
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vchan_cookie_complete(&d->vd);
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}
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} else {
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if (c->cyclic) {
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vchan_cyclic_callback(&d->vd);
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} else if (d->using_ll || c->sgidx == d->sglen) {
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omap_dma_start_desc(c);
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vchan_cookie_complete(&d->vd);
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} else {
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omap_dma_start_sg(c, d);
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}
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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@ -503,6 +621,7 @@ static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct omap_dmadev *od = to_omap_dma_dev(chan->device);
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struct omap_chan *c = to_omap_dma_chan(chan);
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struct device *dev = od->ddev.dev;
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int ret;
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if (od->legacy) {
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@ -513,8 +632,7 @@ static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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&c->dma_ch);
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}
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dev_dbg(od->ddev.dev, "allocating channel %u for %u\n",
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c->dma_ch, c->dma_sig);
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dev_dbg(dev, "allocating channel %u for %u\n", c->dma_ch, c->dma_sig);
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if (ret >= 0) {
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omap_dma_assign(od, c, c->dma_ch);
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@ -570,7 +688,8 @@ static void omap_dma_free_chan_resources(struct dma_chan *chan)
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vchan_free_chan_resources(&c->vc);
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omap_free_dma(c->dma_ch);
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dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
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dev_dbg(od->ddev.dev, "freeing channel %u used for %u\n", c->dma_ch,
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c->dma_sig);
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c->dma_sig = 0;
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}
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@ -744,6 +863,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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struct omap_desc *d;
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dma_addr_t dev_addr;
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unsigned i, es, en, frame_bytes;
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bool ll_failed = false;
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u32 burst;
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if (dir == DMA_DEV_TO_MEM) {
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@ -784,13 +904,16 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->es = es;
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d->ccr = c->ccr | CCR_SYNC_FRAME;
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if (dir == DMA_DEV_TO_MEM)
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if (dir == DMA_DEV_TO_MEM) {
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d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
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else
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d->csdp = CSDP_DST_BURST_64 | CSDP_DST_PACKED;
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} else {
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d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
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d->csdp = CSDP_SRC_BURST_64 | CSDP_SRC_PACKED;
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}
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d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
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d->csdp = es;
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d->csdp |= es;
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if (dma_omap1()) {
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d->cicr |= CICR_TOUT_IE;
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@ -819,14 +942,47 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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*/
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en = burst;
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frame_bytes = es_bytes[es] * en;
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if (sglen >= 2)
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d->using_ll = od->ll123_supported;
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for_each_sg(sgl, sgent, sglen, i) {
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d->sg[i].addr = sg_dma_address(sgent);
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d->sg[i].en = en;
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d->sg[i].fn = sg_dma_len(sgent) / frame_bytes;
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struct omap_sg *osg = &d->sg[i];
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osg->addr = sg_dma_address(sgent);
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osg->en = en;
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osg->fn = sg_dma_len(sgent) / frame_bytes;
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if (d->using_ll) {
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osg->t2_desc = dma_pool_alloc(od->desc_pool, GFP_ATOMIC,
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&osg->t2_desc_paddr);
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if (!osg->t2_desc) {
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dev_err(chan->device->dev,
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"t2_desc[%d] allocation failed\n", i);
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ll_failed = true;
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d->using_ll = false;
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continue;
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}
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omap_dma_fill_type2_desc(d, i, dir, (i == sglen - 1));
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}
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}
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d->sglen = sglen;
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/* Release the dma_pool entries if one allocation failed */
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if (ll_failed) {
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for (i = 0; i < d->sglen; i++) {
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struct omap_sg *osg = &d->sg[i];
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if (osg->t2_desc) {
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dma_pool_free(od->desc_pool, osg->t2_desc,
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osg->t2_desc_paddr);
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osg->t2_desc = NULL;
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}
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}
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}
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return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
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}
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@ -1225,16 +1381,24 @@ static int omap_dma_probe(struct platform_device *pdev)
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spin_lock_init(&od->lock);
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spin_lock_init(&od->irq_lock);
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od->dma_requests = OMAP_SDMA_REQUESTS;
|
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if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
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"dma-requests",
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&od->dma_requests)) {
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if (!pdev->dev.of_node) {
|
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od->dma_requests = od->plat->dma_attr->lch_count;
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if (unlikely(!od->dma_requests))
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od->dma_requests = OMAP_SDMA_REQUESTS;
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} else if (of_property_read_u32(pdev->dev.of_node, "dma-requests",
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&od->dma_requests)) {
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dev_info(&pdev->dev,
|
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"Missing dma-requests property, using %u.\n",
|
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OMAP_SDMA_REQUESTS);
|
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od->dma_requests = OMAP_SDMA_REQUESTS;
|
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}
|
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for (i = 0; i < OMAP_SDMA_CHANNELS; i++) {
|
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od->lch_map = devm_kcalloc(&pdev->dev, od->dma_requests,
|
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sizeof(*od->lch_map), GFP_KERNEL);
|
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if (!od->lch_map)
|
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return -ENOMEM;
|
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|
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for (i = 0; i < od->dma_requests; i++) {
|
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rc = omap_dma_chan_init(od);
|
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if (rc) {
|
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omap_dma_free(od);
|
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@ -1257,10 +1421,25 @@ static int omap_dma_probe(struct platform_device *pdev)
|
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return rc;
|
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}
|
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if (omap_dma_glbl_read(od, CAPS_0) & CAPS_0_SUPPORT_LL123)
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od->ll123_supported = true;
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od->ddev.filter.map = od->plat->slave_map;
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od->ddev.filter.mapcnt = od->plat->slavecnt;
|
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od->ddev.filter.fn = omap_dma_filter_fn;
|
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|
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if (od->ll123_supported) {
|
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od->desc_pool = dma_pool_create(dev_name(&pdev->dev),
|
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&pdev->dev,
|
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sizeof(struct omap_type2_desc),
|
||||
4, 0);
|
||||
if (!od->desc_pool) {
|
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dev_err(&pdev->dev,
|
||||
"unable to allocate descriptor pool\n");
|
||||
od->ll123_supported = false;
|
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}
|
||||
}
|
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|
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rc = dma_async_device_register(&od->ddev);
|
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if (rc) {
|
||||
pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
|
||||
@ -1284,7 +1463,8 @@ static int omap_dma_probe(struct platform_device *pdev)
|
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}
|
||||
}
|
||||
|
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dev_info(&pdev->dev, "OMAP DMA engine driver\n");
|
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dev_info(&pdev->dev, "OMAP DMA engine driver%s\n",
|
||||
od->ll123_supported ? " (LinkedList1/2/3 supported)" : "");
|
||||
|
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return rc;
|
||||
}
|
||||
@ -1307,6 +1487,9 @@ static int omap_dma_remove(struct platform_device *pdev)
|
||||
omap_dma_glbl_write(od, IRQENABLE_L0, 0);
|
||||
}
|
||||
|
||||
if (od->ll123_supported)
|
||||
dma_pool_destroy(od->desc_pool);
|
||||
|
||||
omap_dma_free(od);
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user