crypto: atmel-aes - simplify the configuration of the AES IP
This patch reworks the AES_FLAGS_* to simplify the configuration of the AES IP. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Cyrille Pitchen
Herbert Xu
parent
794595d204
commit
77dacf5fc5
@ -48,22 +48,28 @@
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#define CFB64_BLOCK_SIZE 8
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/* AES flags */
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#define AES_FLAGS_MODE_MASK 0x03ff
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#define AES_FLAGS_ENCRYPT BIT(0)
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#define AES_FLAGS_CBC BIT(1)
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#define AES_FLAGS_CFB BIT(2)
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#define AES_FLAGS_CFB8 BIT(3)
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#define AES_FLAGS_CFB16 BIT(4)
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#define AES_FLAGS_CFB32 BIT(5)
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#define AES_FLAGS_CFB64 BIT(6)
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#define AES_FLAGS_CFB128 BIT(7)
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#define AES_FLAGS_OFB BIT(8)
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#define AES_FLAGS_CTR BIT(9)
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/* Reserve bits [18:16] [14:12] [0] for mode (same as for AES_MR) */
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#define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
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#define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
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#define AES_FLAGS_ECB AES_MR_OPMOD_ECB
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#define AES_FLAGS_CBC AES_MR_OPMOD_CBC
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#define AES_FLAGS_OFB AES_MR_OPMOD_OFB
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#define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
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#define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
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#define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
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#define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
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#define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
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#define AES_FLAGS_CTR AES_MR_OPMOD_CTR
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#define AES_FLAGS_INIT BIT(16)
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#define AES_FLAGS_DMA BIT(17)
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#define AES_FLAGS_BUSY BIT(18)
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#define AES_FLAGS_FAST BIT(19)
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#define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
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AES_FLAGS_ENCRYPT)
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#define AES_FLAGS_INIT BIT(2)
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#define AES_FLAGS_BUSY BIT(3)
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#define AES_FLAGS_DMA BIT(4)
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#define AES_FLAGS_FAST BIT(5)
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#define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY)
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#define ATMEL_AES_QUEUE_LENGTH 50
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@ -306,6 +312,13 @@ static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
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return 0;
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}
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static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
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const struct atmel_aes_reqctx *rctx)
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{
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/* Clear all but persistent flags and set request flags. */
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dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
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}
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static void atmel_aes_finish_req(struct atmel_aes_dev *dd, int err)
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{
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struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
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@ -329,6 +342,34 @@ static int atmel_aes_crypt_dma(struct atmel_aes_dev *dd,
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{
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struct scatterlist sg[2];
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struct dma_async_tx_descriptor *in_desc, *out_desc;
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enum dma_slave_buswidth addr_width;
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u32 maxburst;
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switch (dd->ctx->block_size) {
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case CFB8_BLOCK_SIZE:
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addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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maxburst = 1;
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break;
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case CFB16_BLOCK_SIZE:
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addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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maxburst = 1;
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break;
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case CFB32_BLOCK_SIZE:
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case CFB64_BLOCK_SIZE:
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addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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maxburst = 1;
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break;
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case AES_BLOCK_SIZE:
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addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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maxburst = dd->caps.max_burst_size;
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break;
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default:
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return -EINVAL;
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}
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dd->dma_size = length;
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@ -337,35 +378,13 @@ static int atmel_aes_crypt_dma(struct atmel_aes_dev *dd,
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dma_sync_single_for_device(dd->dev, dma_addr_out, length,
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DMA_FROM_DEVICE);
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if (dd->flags & AES_FLAGS_CFB8) {
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dd->dma_lch_in.dma_conf.dst_addr_width =
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DMA_SLAVE_BUSWIDTH_1_BYTE;
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dd->dma_lch_out.dma_conf.src_addr_width =
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DMA_SLAVE_BUSWIDTH_1_BYTE;
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} else if (dd->flags & AES_FLAGS_CFB16) {
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dd->dma_lch_in.dma_conf.dst_addr_width =
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DMA_SLAVE_BUSWIDTH_2_BYTES;
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dd->dma_lch_out.dma_conf.src_addr_width =
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DMA_SLAVE_BUSWIDTH_2_BYTES;
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} else {
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dd->dma_lch_in.dma_conf.dst_addr_width =
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DMA_SLAVE_BUSWIDTH_4_BYTES;
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dd->dma_lch_out.dma_conf.src_addr_width =
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DMA_SLAVE_BUSWIDTH_4_BYTES;
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}
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dd->dma_lch_in.dma_conf.dst_addr_width = addr_width;
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dd->dma_lch_in.dma_conf.src_maxburst = maxburst;
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dd->dma_lch_in.dma_conf.dst_maxburst = maxburst;
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if (dd->flags & (AES_FLAGS_CFB8 | AES_FLAGS_CFB16 |
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AES_FLAGS_CFB32 | AES_FLAGS_CFB64)) {
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dd->dma_lch_in.dma_conf.src_maxburst = 1;
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dd->dma_lch_in.dma_conf.dst_maxburst = 1;
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dd->dma_lch_out.dma_conf.src_maxburst = 1;
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dd->dma_lch_out.dma_conf.dst_maxburst = 1;
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} else {
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dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size;
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dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size;
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dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size;
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dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size;
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}
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dd->dma_lch_out.dma_conf.src_addr_width = addr_width;
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dd->dma_lch_out.dma_conf.src_maxburst = maxburst;
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dd->dma_lch_out.dma_conf.dst_maxburst = maxburst;
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dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
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dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
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@ -521,30 +540,7 @@ static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
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else
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valmr |= AES_MR_KEYSIZE_256;
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if (dd->flags & AES_FLAGS_CBC) {
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valmr |= AES_MR_OPMOD_CBC;
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} else if (dd->flags & AES_FLAGS_CFB) {
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valmr |= AES_MR_OPMOD_CFB;
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if (dd->flags & AES_FLAGS_CFB8)
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valmr |= AES_MR_CFBS_8b;
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else if (dd->flags & AES_FLAGS_CFB16)
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valmr |= AES_MR_CFBS_16b;
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else if (dd->flags & AES_FLAGS_CFB32)
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valmr |= AES_MR_CFBS_32b;
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else if (dd->flags & AES_FLAGS_CFB64)
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valmr |= AES_MR_CFBS_64b;
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else if (dd->flags & AES_FLAGS_CFB128)
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valmr |= AES_MR_CFBS_128b;
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} else if (dd->flags & AES_FLAGS_OFB) {
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valmr |= AES_MR_OPMOD_OFB;
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} else if (dd->flags & AES_FLAGS_CTR) {
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valmr |= AES_MR_OPMOD_CTR;
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} else {
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valmr |= AES_MR_OPMOD_ECB;
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}
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if (dd->flags & AES_FLAGS_ENCRYPT)
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valmr |= AES_MR_CYPHER_ENC;
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valmr |= dd->flags & AES_FLAGS_MODE_MASK;
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if (use_dma) {
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valmr |= AES_MR_SMOD_IDATAR0;
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@ -559,11 +555,8 @@ static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
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atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
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dd->ctx->keylen >> 2);
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if (((dd->flags & AES_FLAGS_CBC) || (dd->flags & AES_FLAGS_CFB) ||
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(dd->flags & AES_FLAGS_OFB) || (dd->flags & AES_FLAGS_CTR)) &&
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iv) {
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if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
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atmel_aes_write_n(dd, AES_IVR(0), iv, 4);
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}
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}
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static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
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@ -617,8 +610,7 @@ static int atmel_aes_start(struct atmel_aes_dev *dd)
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dd->out_sg = req->dst;
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rctx = ablkcipher_request_ctx(req);
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rctx->mode &= AES_FLAGS_MODE_MASK;
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dd->flags = (dd->flags & ~AES_FLAGS_MODE_MASK) | rctx->mode;
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atmel_aes_set_mode(dd, rctx);
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err = atmel_aes_hw_init(dd);
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if (!err) {
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@ -728,36 +720,26 @@ static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
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struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
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struct atmel_aes_dev *dd;
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if (mode & AES_FLAGS_CFB8) {
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if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) {
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pr_err("request size is not exact amount of CFB8 blocks\n");
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return -EINVAL;
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}
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switch (mode & AES_FLAGS_OPMODE_MASK) {
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case AES_FLAGS_CFB8:
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ctx->block_size = CFB8_BLOCK_SIZE;
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} else if (mode & AES_FLAGS_CFB16) {
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if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) {
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pr_err("request size is not exact amount of CFB16 blocks\n");
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return -EINVAL;
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}
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break;
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case AES_FLAGS_CFB16:
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ctx->block_size = CFB16_BLOCK_SIZE;
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} else if (mode & AES_FLAGS_CFB32) {
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if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) {
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pr_err("request size is not exact amount of CFB32 blocks\n");
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return -EINVAL;
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}
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break;
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case AES_FLAGS_CFB32:
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ctx->block_size = CFB32_BLOCK_SIZE;
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} else if (mode & AES_FLAGS_CFB64) {
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if (!IS_ALIGNED(req->nbytes, CFB64_BLOCK_SIZE)) {
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pr_err("request size is not exact amount of CFB64 blocks\n");
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return -EINVAL;
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}
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break;
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case AES_FLAGS_CFB64:
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ctx->block_size = CFB64_BLOCK_SIZE;
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} else {
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if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
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pr_err("request size is not exact amount of AES blocks\n");
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return -EINVAL;
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}
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break;
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default:
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ctx->block_size = AES_BLOCK_SIZE;
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break;
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}
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dd = atmel_aes_find_dev(ctx);
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@ -857,14 +839,12 @@ static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT);
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return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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0);
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return atmel_aes_crypt(req, AES_FLAGS_ECB);
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}
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static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
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@ -893,62 +873,52 @@ static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
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static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB128);
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return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_CFB | AES_FLAGS_CFB128);
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return atmel_aes_crypt(req, AES_FLAGS_CFB128);
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}
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static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB64);
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return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_CFB | AES_FLAGS_CFB64);
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return atmel_aes_crypt(req, AES_FLAGS_CFB64);
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}
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static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB32);
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return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_CFB | AES_FLAGS_CFB32);
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return atmel_aes_crypt(req, AES_FLAGS_CFB32);
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}
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static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB16);
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return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_CFB | AES_FLAGS_CFB16);
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return atmel_aes_crypt(req, AES_FLAGS_CFB16);
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}
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static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB8);
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return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req,
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AES_FLAGS_CFB | AES_FLAGS_CFB8);
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return atmel_aes_crypt(req, AES_FLAGS_CFB8);
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}
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static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
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