From f249e60eb2c708f66520a025ce06701cea5ca7d9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Jan 2021 20:40:31 +0100 Subject: [PATCH 1/6] dt-bindings: add ebang vendor prefix Add vendor prefix for Zhejiang Ebang Communication Co., Ltd. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20210120194033.26970-2-michael@walle.cc Acked-by: Rob Herring Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 041ae90b0d8f..f21fce7fdff6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -311,6 +311,8 @@ patternProperties: description: Dyna-Image "^ea,.*": description: Embedded Artists AB + "^ebang,.*": + description: Zhejiang Ebang Communication Co., Ltd "^ebs-systart,.*": description: EBS-SYSTART GmbH "^ebv,.*": From 12e6d3eb8e0a8d8cc2b1156af9efb998f0f21941 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Jan 2021 20:40:32 +0100 Subject: [PATCH 2/6] dt-bindings: arm: add Ebang EBAZ4205 board Add the Ebang EBAZ4205 board to the Zynq-7000 board category. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20210120194033.26970-3-michael@walle.cc Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/arm/xilinx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index e0c6787f6e94..aaca69d0199f 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -22,6 +22,7 @@ properties: - adapteva,parallella - digilent,zynq-zybo - digilent,zynq-zybo-z7 + - ebang,ebaz4205 - xlnx,zynq-cc108 - xlnx,zynq-zc702 - xlnx,zynq-zc706 From 00c2747814cc0067c7603c06dcef26a583cfe489 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Jan 2021 20:40:33 +0100 Subject: [PATCH 3/6] ARM: dts: add Ebang EBAZ4205 device tree The Ebang EBAZ4205 is a simple board based on the Xilinx Zynq-7000 SoC. Its features are: - one serial port - 256 MB RAM - 128 MB NAND flash - SDcard slot - IP101GA 10/100 Mbit Ethernet PHY (connected to PL IOs) - two LEDs (connected to PL IOs) - one Push Button (connect to PL IOs) - (optional) RTC - (optional) Input voltage supervisor The NAND flash is not supported in mainline linux yet. Unfortunately, the PHY is connected via the PL, thus for working ethernet the FPGA has to be configured. Also, depending on the board variant, the PHY has no external crystal and its clock needs to be driven by the PL. FCLK3 is used for this and is kept enabled. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20210120194033.26970-4-michael@walle.cc Signed-off-by: Michal Simek --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-ebaz4205.dts | 109 ++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-ebaz4205.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3d1ea0b25168..2cbb4e9a6dfa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1307,6 +1307,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts new file mode 100644 index 000000000000..e802d4ae8804 --- /dev/null +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Michael Walle + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Ebang EBAZ4205"; + compatible = "ebang,ebaz4205", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <8>; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <&phy>; + + /* PHY clock */ + assigned-clocks = <&clkc 18>; + assigned-clock-rates = <25000000>; + + phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pinctrl0 { + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_34_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_34_grp"; + io-standard = <3>; + slew-rate = <0>; + bias-high-impedance; + bias-pull-up; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_4_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_4_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; From 10d43c861476978389e370eed177ba8a18f8146c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 1 Feb 2021 14:30:00 +0100 Subject: [PATCH 4/6] ARM: dts: ebaz4205: add pinctrl entries for switches Add the pinctrl entries for the GPIOs which are connected to the push buttons on this board. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20210201133000.23402-1-michael@walle.cc Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-ebaz4205.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts index e802d4ae8804..b0b836aedd76 100644 --- a/arch/arm/boot/dts/zynq-ebaz4205.dts +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts @@ -43,7 +43,30 @@ }; }; +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &pinctrl0 { + pinctrl_gpio0_default: gpio0-default { + mux { + groups = "gpio0_20_grp", "gpio0_32_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_20_grp", "gpio0_32_grp"; + io-standard = <3>; + slew-rate = <0>; + }; + + conf-pull-up { + pins = "MIO20", "MIO32"; + bias-disable; + }; + }; + pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; From 9cc5c6c1567cb46bca1362c6e1f66edbeb3478bc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 1 Feb 2021 14:16:12 +0100 Subject: [PATCH 5/6] dt-bindings: arm: xilinx: Add missing Zturn boards Add missing DT compatible strings for Zturn boards. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f6f642d75c1b1160ed78f6de0a2944ab64017691.1612185370.git.michal.simek@xilinx.com Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index aaca69d0199f..05217537fb0c 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -23,6 +23,8 @@ properties: - digilent,zynq-zybo - digilent,zynq-zybo-z7 - ebang,ebaz4205 + - myir,zynq-zturn-v5 + - myir,zynq-zturn - xlnx,zynq-cc108 - xlnx,zynq-zc702 - xlnx,zynq-zc706 From 19e1f484a6bb452d28d79cf41f280cdfde3176a9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 10 Feb 2021 11:10:25 +0100 Subject: [PATCH 6/6] dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml Convert spi-zynq-qspi.txt to yaml. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4ece21a7e9691ed1e775fd6b0b4046b1562e44bd.1612951821.git.michal.simek@xilinx.com Reviewed-by: Rob Herring --- .../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 -------- .../bindings/spi/xlnx,zynq-qspi.yaml | 59 +++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 60 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt create mode 100644 Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt deleted file mode 100644 index 16b734ad3102..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt +++ /dev/null @@ -1,25 +0,0 @@ -Xilinx Zynq QSPI controller Device Tree Bindings -------------------------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,zynq-qspi-1.0". -- reg : Physical base address and size of QSPI registers map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "ref_clk", "pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). - -Optional properties: -- num-cs : Number of chip selects used. - -Example: - qspi: spi@e000d000 { - compatible = "xlnx,zynq-qspi-1.0"; - reg = <0xe000d000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <0 19 4>; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 10>, <&clkc 43>; - num-cs = <1>; - }; diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml new file mode 100644 index 000000000000..1f1c40a9f320 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq QSPI controller + +description: + The Xilinx Zynq QSPI controller is used to access multi-bit serial flash + memory devices. + +allOf: + - $ref: "spi-controller.yaml#" + +maintainers: + - Michal Simek + +# Everything else is described in the common file +properties: + compatible: + const: xlnx,zynq-qspi-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: reference clock + - description: peripheral clock + + clock-names: + items: + - const: ref_clk + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + spi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + reg = <0xe000d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + clock-names = "ref_clk", "pclk"; + clocks = <&clkc 10>, <&clkc 43>; + num-cs = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 546aa66428c9..e494b061dcd1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2766,6 +2766,7 @@ W: http://wiki.xilinx.com T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ F: drivers/block/xsysace.c F: drivers/clocksource/timer-cadence-ttc.c