Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"The irq departement delivers:
- a cleanup series to get rid of mindlessly copied code.
- another bunch of new pointlessly different interrupt chip drivers.
Adding homebrewn irq chips (and timers) to SoCs must provide a
value add which is beyond the imagination of mere mortals.
- the usual SoC irq controller updates, IOW my second cat herding
project"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
irqchip: gic-v3: Implement CPU PM notifier
irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling
irqchip: renesas-intc-irqpin: Add minimal runtime PM support
irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev
irqchip: atmel-aic5: Add sama5d4 support
irqchip: atmel-aic5: The sama5d3 has 48 IRQs
Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller
irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs
irqchip: renesas-irqc: Add DT binding documentation
irqchip: renesas-intc-irqpin: Document SoC-specific bindings
openrisc: Get rid of handle_IRQ
arm64: Get rid of handle_IRQ
ARM: omap2: irq: Convert to handle_domain_irq
ARM: imx: tzic: Convert to handle_domain_irq
ARM: imx: avic: Convert to handle_domain_irq
irqchip: or1k-pic: Convert to handle_domain_irq
irqchip: atmel-aic5: Convert to handle_domain_irq
irqchip: atmel-aic: Convert to handle_domain_irq
irqchip: gic-v3: Convert to handle_domain_irq
...
This commit is contained in:
Linus Torvalds
@ -2,7 +2,7 @@
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Required properties:
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- compatible: Should be "atmel,<chip>-aic"
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<chip> can be "at91rm9200" or "sama5d3"
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<chip> can be "at91rm9200", "sama5d3" or "sama5d4"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- interrupt-parent: For single AIC system, it is an empty property.
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- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
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@ -0,0 +1,86 @@
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Broadcom BCM7120-style Level 2 interrupt controller
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This interrupt controller hardware is a second level interrupt controller that
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is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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platforms. It can be found on BCM7xxx products starting with BCM7120.
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Such an interrupt controller has the following hardware design:
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- outputs multiple interrupts signals towards its interrupt controller parent
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- controls how some of the interrupts will be flowing, whether they will
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directly output an interrupt signal towards the interrupt controller parent,
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or if they will output an interrupt signal at this 2nd level interrupt
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controller, in particular for UARTs
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- not all 32-bits within the interrupt controller actually map to an interrupt
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The typical hardware layout for this controller is represented below:
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2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
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0 -----[ MUX ] ------------|==========> GIC interrupt 75
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\-----------\
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1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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\------------|
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2 -----[ MUX ] --------)---|==========> GIC interrupt 77
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\------------|
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3 ---------------------|
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4 ---------------------|
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5 ---------------------|
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7 ---------------------|---|===========> GIC interrupt 66
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9 ---------------------|
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10 --------------------|
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11 --------------------/
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6 ------------------------\
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|===========> GIC interrupt 64
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8 ------------------------/
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12 ........................ X
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13 ........................ X (not connected)
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..
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31 ........................ X
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Required properties:
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- compatible: should be "brcm,bcm7120-l2-intc"
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- reg: specifies the base physical address and size of the registers
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this one is cascaded from
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- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
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node, valid values depend on the type of parent interrupt controller
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- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
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are wired to this 2nd level interrupt controller, and how they match their
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respective interrupt parents. Should match exactly the number of interrupts
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specified in the 'interrupts' property.
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Optional properties:
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- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
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wakeup source for system suspend/resume.
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- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
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interrupts which have a mux gate, typically UARTs. Setting these bits will
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make their respective interrupts outputs bypass this 2nd level interrupt
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controller completely, it completely transparent for the interrupt controller
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parent
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Example:
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irq0_intc: interrupt-controller@f0406800 {
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compatible = "brcm,bcm7120-l2-intc";
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interrupt-parent = <&intc>;
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#interrupt-cells = <1>;
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reg = <0xf0406800 0x8>;
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interrupt-controller;
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interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
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brcm,int-map-mask = <0xeb8>, <0x140>;
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brcm,int-fwd-mask = <0x7>;
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};
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@ -2,7 +2,13 @@ DT bindings for the R-/SH-Mobile irqpin controller
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Required properties:
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- compatible: has to be "renesas,intc-irqpin"
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- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
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as fallback.
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Examples with soctypes are:
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- "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
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- "renesas,intc-irqpin-r8a7778" (R-Car M1A)
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- "renesas,intc-irqpin-r8a7779" (R-Car H1)
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- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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@ -0,0 +1,32 @@
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DT bindings for the R-Mobile/R-Car interrupt controller
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Required properties:
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- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
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Examples with soctypes are:
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- "renesas,irqc-r8a73a4" (R-Mobile AP6)
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- "renesas,irqc-r8a7790" (R-Car H2)
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- "renesas,irqc-r8a7791" (R-Car M2-W)
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- "renesas,irqc-r8a7792" (R-Car V2H)
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- "renesas,irqc-r8a7793" (R-Car M2-N)
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- "renesas,irqc-r8a7794" (R-Car E2)
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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Example:
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7790", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -0,0 +1,36 @@
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Keystone 2 IRQ controller IP
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On Keystone SOCs, DSP cores can send interrupts to ARM
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host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
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The IRQ handler running on HOST OS can identify DSP signal source by
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analyzing SRCCx bits in IPCARx registers. This is one of the component
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used by the IPC mechanism used on Keystone SOCs.
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Required Properties:
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- compatible: should be "ti,keystone-irq"
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- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
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access device control registers and the offset inside
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device control registers range.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source should be 1.
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- interrupts: interrupt reference to primary interrupt controller
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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Example:
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kirq0: keystone_irq0@026202a0 {
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compatible = "ti,keystone-irq";
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ti,syscon-dev = <&devctrl 0x2a0>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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dsp0: dsp0 {
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compatible = "linux,rproc-user";
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...
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interrupt-parent = <&kirq0>;
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interrupts = <10 2>;
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};
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