clk: qcom: gdsc: Implement NO_RET_PERIPH flag
In some rare occasions, we want to only set the RETAIN_MEM bit, but not the RETAIN_PERIPH one: this is seen on at least SDM630/636/660's GPU-GX GDSC, where unsetting and setting back the RETAIN_PERIPH bit will generate chaos and panics during GPU suspend time (mainly, the chaos is unaligned access). For this reason, introduce a new NO_RET_PERIPH flag to the GDSC driver to address this corner case. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-8-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -183,7 +183,10 @@ static inline int gdsc_assert_reset(struct gdsc *sc)
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static inline void gdsc_force_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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u32 mask = RETAIN_MEM;
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if (!(sc->flags & NO_RET_PERIPH))
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mask |= RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
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@ -192,7 +195,10 @@ static inline void gdsc_force_mem_on(struct gdsc *sc)
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static inline void gdsc_clear_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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u32 mask = RETAIN_MEM;
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if (!(sc->flags & NO_RET_PERIPH))
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mask |= RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
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@ -42,7 +42,7 @@ struct gdsc {
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#define PWRSTS_ON BIT(2)
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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const u8 flags;
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const u16 flags;
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#define VOTABLE BIT(0)
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#define CLAMP_IO BIT(1)
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#define HW_CTRL BIT(2)
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@ -51,6 +51,7 @@ struct gdsc {
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#define POLL_CFG_GDSCR BIT(5)
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#define ALWAYS_ON BIT(6)
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#define RETAIN_FF_ENABLE BIT(7)
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#define NO_RET_PERIPH BIT(8)
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struct reset_controller_dev *rcdev;
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unsigned int *resets;
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unsigned int reset_count;
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