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perf vendor events: Add westmereex counter information

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Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
475892a969
and later patches.

Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-38-irogers@google.com
This commit is contained in:
Ian Rogers 2024-06-20 11:17:51 -07:00 committed by Namhyung Kim
parent dc5f18a102
commit 788c516052
8 changed files with 586 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

320
tools/perf/pmu-events/arch/x86/westmereex/cache.json
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File diff suppressed because it is too large Load Diff

7
tools/perf/pmu-events/arch/x86/westmereex/counter.json Normal file
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@ -0,0 +1,7 @@
[
{
"Unit": "core",
"CountersNumFixed": "4",
"CountersNumGeneric": "4"
}
]

28
tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
@ -9,6 +10,7 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
@ -17,6 +19,7 @@
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
@ -25,6 +28,7 @@
},
{
"BriefDescription": "MMX Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
@ -32,6 +36,7 @@
},
{
"BriefDescription": "SSE2 integer Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
@ -39,6 +44,7 @@
},
{
"BriefDescription": "SSE* FP double precision Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
@ -46,6 +52,7 @@
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
@ -53,6 +60,7 @@
},
{
"BriefDescription": "SSE FP packed Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
@ -60,6 +68,7 @@
},
{
"BriefDescription": "SSE FP scalar Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
@ -67,6 +76,7 @@
},
{
"BriefDescription": "SSE* FP single precision Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
@ -74,6 +84,7 @@
},
{
"BriefDescription": "Computational floating-point operations executed",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
@ -81,6 +92,7 @@
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
@ -88,6 +100,7 @@
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
@ -95,6 +108,7 @@
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
@ -102,6 +116,7 @@
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
@ -109,6 +124,7 @@
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
@ -116,6 +132,7 @@
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@ -123,6 +140,7 @@
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
@ -130,6 +148,7 @@
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
@ -137,6 +156,7 @@
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@ -144,6 +164,7 @@
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
@ -151,6 +172,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
@ -158,6 +180,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
@ -165,6 +188,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
@ -172,6 +196,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
@ -179,6 +204,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
@ -186,6 +212,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
@ -193,6 +220,7 @@
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",

3
tools/perf/pmu-events/arch/x86/westmereex/frontend.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "Instructions decoded",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Macro-fused instructions decoded",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "Two Uop instructions decoded",
"Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",

68
tools/perf/pmu-events/arch/x86/westmereex/memory.json
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@ -1,6 +1,7 @@
[
{
"BriefDescription": "Misaligned store references",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.STORE",
"SampleAfterValue": "200000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -17,6 +19,7 @@
},
{
"BriefDescription": "Offcore data reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -26,6 +29,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -35,6 +39,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -44,6 +49,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -53,6 +59,7 @@
},
{
"BriefDescription": "Offcore code reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -62,6 +69,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -71,6 +79,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -80,6 +89,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -89,6 +99,7 @@
},
{
"BriefDescription": "Offcore requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -98,6 +109,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -107,6 +119,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -116,6 +129,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -125,6 +139,7 @@
},
{
"BriefDescription": "Offcore RFO requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -134,6 +149,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -143,6 +159,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -152,6 +169,7 @@
},
{
"BriefDescription": "Offcore writebacks to any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -161,6 +179,7 @@
},
{
"BriefDescription": "Offcore writebacks that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -170,6 +189,7 @@
},
{
"BriefDescription": "Offcore writebacks to the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -179,6 +199,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -188,6 +209,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -197,6 +219,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -206,6 +229,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -215,6 +239,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -224,6 +249,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -233,6 +259,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any LLC miss",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -242,6 +269,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -251,6 +279,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -260,6 +289,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -269,6 +299,7 @@
},
{
"BriefDescription": "Offcore demand data requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -278,6 +309,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -287,6 +319,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -296,6 +329,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -305,6 +339,7 @@
},
{
"BriefDescription": "Offcore demand data reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -314,6 +349,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -323,6 +359,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -332,6 +369,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -341,6 +379,7 @@
},
{
"BriefDescription": "Offcore demand code reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -350,6 +389,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -359,6 +399,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -368,6 +409,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -377,6 +419,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -386,6 +429,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -395,6 +439,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -404,6 +449,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -413,6 +459,7 @@
},
{
"BriefDescription": "Offcore other requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -422,6 +469,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -431,6 +479,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -440,6 +489,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -449,6 +499,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -458,6 +509,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -467,6 +519,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -476,6 +529,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -485,6 +539,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -494,6 +549,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -503,6 +559,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -512,6 +569,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -521,6 +579,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -530,6 +589,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -539,6 +599,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -548,6 +609,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -557,6 +619,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -566,6 +629,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1A6",
@ -575,6 +639,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1A6",
@ -584,6 +649,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that missed the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1A6",
@ -593,6 +659,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1A6",
@ -602,6 +669,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1A6",

28
tools/perf/pmu-events/arch/x86/westmereex/other.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "I/O transactions",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
@ -36,6 +41,7 @@
},
{
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
@ -43,6 +49,7 @@
},
{
"BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
@ -50,6 +57,7 @@
},
{
"BriefDescription": "Loads that partially overlap an earlier store",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
@ -57,6 +65,7 @@
},
{
"BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
@ -64,6 +73,7 @@
},
{
"BriefDescription": "Loads dispatched from the MOB",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
@ -71,6 +81,7 @@
},
{
"BriefDescription": "Loads dispatched that bypass the MOB",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
@ -78,6 +89,7 @@
},
{
"BriefDescription": "Loads dispatched from stage 305",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
@ -85,6 +97,7 @@
},
{
"BriefDescription": "False dependencies due to partial address aliasing",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
@ -92,6 +105,7 @@
},
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
@ -99,6 +113,7 @@
},
{
"BriefDescription": "Segment rename stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
@ -106,6 +121,7 @@
},
{
"BriefDescription": "Snoop code requests",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
@ -113,6 +129,7 @@
},
{
"BriefDescription": "Snoop data requests",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
@ -120,6 +137,7 @@
},
{
"BriefDescription": "Snoop invalidate requests",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
@ -127,6 +145,7 @@
},
{
"BriefDescription": "Outstanding snoop code requests",
"Counter": "0",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
"SampleAfterValue": "2000000",
@ -134,6 +153,7 @@
},
{
"BriefDescription": "Cycles snoop code requests queued",
"Counter": "0",
"CounterMask": "1",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
@ -142,6 +162,7 @@
},
{
"BriefDescription": "Outstanding snoop data requests",
"Counter": "0",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
"SampleAfterValue": "2000000",
@ -149,6 +170,7 @@
},
{
"BriefDescription": "Cycles snoop data requests queued",
"Counter": "0",
"CounterMask": "1",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
@ -157,6 +179,7 @@
},
{
"BriefDescription": "Outstanding snoop invalidate requests",
"Counter": "0",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
"SampleAfterValue": "2000000",
@ -164,6 +187,7 @@
},
{
"BriefDescription": "Cycles snoop invalidate requests queued",
"Counter": "0",
"CounterMask": "1",
"EventCode": "0xB3",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
@ -172,6 +196,7 @@
},
{
"BriefDescription": "Thread responded HIT to snoop",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
@ -179,6 +204,7 @@
},
{
"BriefDescription": "Thread responded HITE to snoop",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
@ -186,6 +212,7 @@
},
{
"BriefDescription": "Thread responded HITM to snoop",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
@ -193,6 +220,7 @@
},
{
"BriefDescription": "Super Queue full stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",

111
tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles the divider is busy",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "Divide Operations executed",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
@ -18,6 +20,7 @@
},
{
"BriefDescription": "Multiply operations executed",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
@ -25,6 +28,7 @@
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
@ -32,6 +36,7 @@
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
@ -39,6 +44,7 @@
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
@ -46,6 +52,7 @@
},
{
"BriefDescription": "Early Branch Prediction Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
@ -53,6 +60,7 @@
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
"Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
@ -60,6 +68,7 @@
},
{
"BriefDescription": "Branch prediction unit missed call or return",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
@ -67,6 +76,7 @@
},
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@ -74,6 +84,7 @@
},
{
"BriefDescription": "Branch instructions executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
@ -81,6 +92,7 @@
},
{
"BriefDescription": "Conditional branch instructions executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
@ -88,6 +100,7 @@
},
{
"BriefDescription": "Unconditional branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
@ -95,6 +108,7 @@
},
{
"BriefDescription": "Unconditional call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@ -102,6 +116,7 @@
},
{
"BriefDescription": "Indirect call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
@ -109,6 +124,7 @@
},
{
"BriefDescription": "Indirect non call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
@ -116,6 +132,7 @@
},
{
"BriefDescription": "Call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
@ -123,6 +140,7 @@
},
{
"BriefDescription": "All non call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
@ -130,6 +148,7 @@
},
{
"BriefDescription": "Indirect return branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
@ -137,6 +156,7 @@
},
{
"BriefDescription": "Taken branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
@ -144,6 +164,7 @@
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@ -152,6 +173,7 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@ -160,6 +182,7 @@
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@ -168,6 +191,7 @@
},
{
"BriefDescription": "Mispredicted branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
@ -175,6 +199,7 @@
},
{
"BriefDescription": "Mispredicted conditional branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
@ -182,6 +207,7 @@
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
@ -189,6 +215,7 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@ -196,6 +223,7 @@
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
@ -203,6 +231,7 @@
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
@ -210,6 +239,7 @@
},
{
"BriefDescription": "Mispredicted call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
@ -217,6 +247,7 @@
},
{
"BriefDescription": "Mispredicted non call branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
@ -224,6 +255,7 @@
},
{
"BriefDescription": "Mispredicted return branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
@ -231,6 +263,7 @@
},
{
"BriefDescription": "Mispredicted taken branches executed",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
@ -238,6 +271,7 @@
},
{
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@ -246,6 +280,7 @@
},
{
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@ -254,6 +289,7 @@
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@ -262,11 +298,13 @@
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
"Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
@ -274,17 +312,20 @@
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
"Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
@ -293,6 +334,7 @@
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
@ -300,6 +342,7 @@
},
{
"BriefDescription": "Instruction Queue full stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@ -307,6 +350,7 @@
},
{
"BriefDescription": "Length Change Prefix stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
@ -314,6 +358,7 @@
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
@ -321,6 +366,7 @@
},
{
"BriefDescription": "Regen stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
@ -328,6 +374,7 @@
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
@ -335,6 +382,7 @@
},
{
"BriefDescription": "Instructions written to instruction queue.",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
@ -342,6 +390,7 @@
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
@ -349,11 +398,13 @@
},
{
"BriefDescription": "Instructions retired (fixed counter)",
"Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
@ -362,6 +413,7 @@
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
@ -370,6 +422,7 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
"Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
@ -380,6 +433,7 @@
},
{
"BriefDescription": "Total cycles (Precise Event)",
"Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@ -390,6 +444,7 @@
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
@ -398,6 +453,7 @@
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
"Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
@ -405,6 +461,7 @@
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
@ -413,6 +470,7 @@
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
@ -422,6 +480,7 @@
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
@ -429,6 +488,7 @@
},
{
"BriefDescription": "Cycles machine clear asserted",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
@ -436,6 +496,7 @@
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
@ -443,6 +504,7 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
@ -450,6 +512,7 @@
},
{
"BriefDescription": "All RAT stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
@ -457,6 +520,7 @@
},
{
"BriefDescription": "Flag stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
@ -464,6 +528,7 @@
},
{
"BriefDescription": "Partial register stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
@ -471,6 +536,7 @@
},
{
"BriefDescription": "ROB read port stalls cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
@ -478,6 +544,7 @@
},
{
"BriefDescription": "Scoreboard stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
@ -485,6 +552,7 @@
},
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
@ -492,6 +560,7 @@
},
{
"BriefDescription": "FPU control word write stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
@ -499,6 +568,7 @@
},
{
"BriefDescription": "Load buffer stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
@ -506,6 +576,7 @@
},
{
"BriefDescription": "MXCSR rename stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
@ -513,6 +584,7 @@
},
{
"BriefDescription": "Other Resource related stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
@ -520,6 +592,7 @@
},
{
"BriefDescription": "ROB full stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
@ -527,6 +600,7 @@
},
{
"BriefDescription": "Reservation Station full stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
@ -534,6 +608,7 @@
},
{
"BriefDescription": "Store buffer stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
@ -541,6 +616,7 @@
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
@ -549,6 +625,7 @@
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
@ -557,6 +634,7 @@
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
@ -565,6 +643,7 @@
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
@ -573,6 +652,7 @@
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
@ -581,6 +661,7 @@
},
{
"BriefDescription": "Stack pointer instructions decoded",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
@ -588,6 +669,7 @@
},
{
"BriefDescription": "Stack pointer sync operations",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
@ -595,6 +677,7 @@
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@ -603,6 +686,7 @@
},
{
"BriefDescription": "Cycles no Uops are decoded",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
@ -613,6 +697,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@ -622,6 +707,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@ -630,6 +716,7 @@
},
{
"BriefDescription": "Uops executed on any port (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@ -640,6 +727,7 @@
},
{
"BriefDescription": "Uops executed on ports 0-4 (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
@ -651,6 +739,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@ -661,6 +750,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@ -670,6 +760,7 @@
},
{
"BriefDescription": "Uops executed on port 0",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
@ -677,6 +768,7 @@
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
@ -684,6 +776,7 @@
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@ -693,6 +786,7 @@
},
{
"BriefDescription": "Uops executed on port 1",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
@ -701,6 +795,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
@ -709,6 +804,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
@ -717,6 +813,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
@ -725,6 +822,7 @@
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
@ -732,6 +830,7 @@
},
{
"BriefDescription": "Uops executed on port 5",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
@ -739,6 +838,7 @@
},
{
"BriefDescription": "Uops issued",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
@ -747,6 +847,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@ -757,6 +858,7 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@ -765,6 +867,7 @@
},
{
"BriefDescription": "Fused Uops issued",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
@ -772,6 +875,7 @@
},
{
"BriefDescription": "Cycles no Uops were issued",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@ -781,6 +885,7 @@
},
{
"BriefDescription": "Cycles Uops are being retired",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@ -790,6 +895,7 @@
},
{
"BriefDescription": "Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
@ -798,6 +904,7 @@
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
@ -806,6 +913,7 @@
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@ -814,6 +922,7 @@
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@ -824,6 +933,7 @@
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
"Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@ -834,6 +944,7 @@
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
"Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",

21
tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
View File

@ -1,6 +1,7 @@
[
{
"BriefDescription": "DTLB load misses",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
@ -8,6 +9,7 @@
},
{
"BriefDescription": "DTLB load miss large page walks",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -15,6 +17,7 @@
},
{
"BriefDescription": "DTLB load miss caused by low part of address",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@ -22,6 +25,7 @@
},
{
"BriefDescription": "DTLB second level hit",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
@ -29,6 +33,7 @@
},
{
"BriefDescription": "DTLB load miss page walks complete",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -36,6 +41,7 @@
},
{
"BriefDescription": "DTLB load miss page walk cycles",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
@ -43,6 +49,7 @@
},
{
"BriefDescription": "DTLB misses",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
@ -50,6 +57,7 @@
},
{
"BriefDescription": "DTLB miss large page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -57,6 +65,7 @@
},
{
"BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
@ -64,6 +73,7 @@
},
{
"BriefDescription": "DTLB first level misses but second level hit",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
@ -71,6 +81,7 @@
},
{
"BriefDescription": "DTLB miss page walks",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -78,6 +89,7 @@
},
{
"BriefDescription": "DTLB miss page walk cycles",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@ -85,6 +97,7 @@
},
{
"BriefDescription": "Extended Page Table walk cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
@ -92,6 +105,7 @@
},
{
"BriefDescription": "ITLB flushes",
"Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
@ -99,6 +113,7 @@
},
{
"BriefDescription": "ITLB miss",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
@ -106,6 +121,7 @@
},
{
"BriefDescription": "ITLB miss large page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -113,6 +129,7 @@
},
{
"BriefDescription": "ITLB miss page walks",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
@ -120,6 +137,7 @@
},
{
"BriefDescription": "ITLB miss page walk cycles",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
@ -127,6 +145,7 @@
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
@ -135,6 +154,7 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@ -143,6 +163,7 @@
},
{
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",