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mmc: mmci: Retry the busy start condition

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This makes the ux500 ->busy_complete() callback re-read
the status register 10 times while waiting for the busy
signal to assert in the status register.

If this does not happen, we bail out regarding the
command completed already, i.e. before we managed to
start to check the busy status.

There is a comment in the code about this, let's just
implement it to be certain that we can catch this glitch
if it happens.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230405-pl180-busydetect-fix-v7-6-69a7164f2a61@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Linus Walleij 2023-06-16 22:42:24 +02:00 committed by Ulf Hansson
parent 7be5ac5f7a
commit 7892497f1f
1 changed files with 27 additions and 12 deletions
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39
drivers/mmc/host/mmci.c
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@ -674,6 +674,7 @@ static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
{ {
void __iomem *base = host->base; void __iomem *base = host->base;
int retries = 10;
if (status & err_msk) { if (status & err_msk) {
/* Stop any ongoing busy detection if an error occurs */ /* Stop any ongoing busy detection if an error occurs */
@ -694,21 +695,35 @@ static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
* Note that, the card may need a couple of clock cycles before * Note that, the card may need a couple of clock cycles before
* it starts signaling busy on DAT0, hence re-read the * it starts signaling busy on DAT0, hence re-read the
* MMCISTATUS register here, to allow the busy bit to be set. * MMCISTATUS register here, to allow the busy bit to be set.
* Potentially we may even need to poll the register for a
* while, to allow it to be set, but tests indicates that it
* isn't needed.
*/ */
if (host->busy_state == MMCI_BUSY_DONE) { if (host->busy_state == MMCI_BUSY_DONE) {
status = readl(base + MMCISTATUS); /*
if (status & host->variant->busy_detect_flag) { * Save the first status register read to be sure to catch
writel(readl(base + MMCIMASK0) | * all bits that may be lost will retrying. If the command
host->variant->busy_detect_mask, * is still busy this will result in assigning 0 to
base + MMCIMASK0); * host->busy_status, which is what it should be in IDLE.
*/
host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; while (retries) {
return false; status = readl(base + MMCISTATUS);
/* Keep accumulating status bits */
host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
if (status & host->variant->busy_detect_flag) {
writel(readl(base + MMCIMASK0) |
host->variant->busy_detect_mask,
base + MMCIMASK0);
host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ;
return false;
}
retries--;
} }
dev_dbg(mmc_dev(host->mmc), "no busy signalling in time\n");
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
writel(readl(base + MMCIMASK0) &
~host->variant->busy_detect_mask, base + MMCIMASK0);
host->busy_state = MMCI_BUSY_DONE;
host->busy_status = 0;
return true;
} }
/* /*