iio: imu: fxos8700: fix incorrect ODR mode readback
The absence of a correct offset leads an incorrect ODR mode readback after use a hexadecimal number to mark the value from FXOS8700_CTRL_REG1. Get ODR mode by field mask and FIELD_GET clearly and conveniently. And attach other additional fix for keeping the original code logic and a good readability. Fixes: 84e5ddd5c46e ("iio: imu: Add support for the FXOS8700 IMU") Signed-off-by: Carlos Song <carlos.song@nxp.com> Link: https://lore.kernel.org/r/20230118074227.1665098-2-carlos.song@nxp.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -10,6 +10,7 @@
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#include <linux/regmap.h>
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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@ -144,9 +145,9 @@
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#define FXOS8700_NVM_DATA_BNK0 0xa7
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/* Bit definitions for FXOS8700_CTRL_REG1 */
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#define FXOS8700_CTRL_ODR_MSK 0x38
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#define FXOS8700_CTRL_ODR_MAX 0x00
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#define FXOS8700_CTRL_ODR_MIN GENMASK(4, 3)
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#define FXOS8700_CTRL_ODR_MSK GENMASK(5, 3)
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/* Bit definitions for FXOS8700_M_CTRL_REG1 */
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#define FXOS8700_HMS_MASK GENMASK(1, 0)
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@ -508,10 +509,9 @@ static int fxos8700_set_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
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if (i >= odr_num)
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return -EINVAL;
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return regmap_update_bits(data->regmap,
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FXOS8700_CTRL_REG1,
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FXOS8700_CTRL_ODR_MSK + FXOS8700_ACTIVE,
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fxos8700_odr[i].bits << 3 | active_mode);
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val &= ~FXOS8700_CTRL_ODR_MSK;
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val |= FIELD_PREP(FXOS8700_CTRL_ODR_MSK, fxos8700_odr[i].bits) | FXOS8700_ACTIVE;
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return regmap_write(data->regmap, FXOS8700_CTRL_REG1, val);
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}
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static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
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@ -524,7 +524,7 @@ static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
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if (ret)
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return ret;
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val &= FXOS8700_CTRL_ODR_MSK;
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val = FIELD_GET(FXOS8700_CTRL_ODR_MSK, val);
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for (i = 0; i < odr_num; i++)
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if (val == fxos8700_odr[i].bits)
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