ARM: late SoC changes for 6.9
These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing.
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Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann:
"These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing"
* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
soc: fsl: dpio: fix kcalloc() argument order
bus: ts-nbus: Improve error reporting
bus: ts-nbus: Convert to atomic pwm API
riscv: dts: starfive: jh7110: Add camera subsystem nodes
ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
dt-bindings: riscv: cpus: reg matches hart ID
reset: Instantiate reset GPIO controller for shared reset-gpios
reset: gpio: Add GPIO-based reset controller
cpufreq: do not open-code of_phandle_args_equal()
of: Add of_phandle_args_equal() helper
reset: simple: add support for Sophgo SG2042
dt-bindings: reset: sophgo: support SG2042
riscv: dts: microchip: add specific compatible for mpfs pdma
riscv: dts: microchip: add missing CAN bus clocks
ARM: brcmstb: Add debug UART entry for 74165
...
This commit is contained in:
Linus Torvalds
commit
78c3925c04
@ -18,6 +18,7 @@ properties:
|
||||
- const: brcm,gisb-arb
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||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm74165-gisb-arb # for V7 new style 16nm chips
|
||||
- brcm,bcm7278-gisb-arb # for V7 28nm chips
|
||||
- brcm,bcm7435-gisb-arb # for newer 40nm chips
|
||||
- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
|
||||
|
||||
56
Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
Normal file
56
Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: OpenCores PWM controller
|
||||
|
||||
maintainers:
|
||||
- William Qiu <william.qiu@starfivetech.com>
|
||||
|
||||
description:
|
||||
The OpenCores PTC ip core contains a PWM controller. When operating in PWM
|
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mode, the PTC core generates binary signal with user-programmable low and
|
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high periods. All PTC counters and registers are 32-bit.
|
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|
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allOf:
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- $ref: pwm.yaml#
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properties:
|
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compatible:
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items:
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||||
- enum:
|
||||
- starfive,jh7100-pwm
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- starfive,jh7110-pwm
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- starfive,jh8100-pwm
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- const: opencores,pwm-v1
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||||
|
||||
reg:
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||||
maxItems: 1
|
||||
|
||||
clocks:
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||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
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||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pwm@12490000 {
|
||||
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
|
||||
reg = <0x12490000 0x10000>;
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||||
clocks = <&clkgen 181>;
|
||||
resets = <&rstgen 109>;
|
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#pwm-cells = <3>;
|
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};
|
||||
@ -0,0 +1,35 @@
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||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sophgo SG2042 SoC Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Chen Wang <unicorn_wang@outlook.com>
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|
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properties:
|
||||
compatible:
|
||||
const: sophgo,sg2042-reset
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||||
|
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reg:
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||||
maxItems: 1
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||||
|
||||
"#reset-cells":
|
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const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rstgen: reset-controller@c00 {
|
||||
compatible = "sophgo,sg2042-reset";
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reg = <0xc00 0xc>;
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#reset-cells = <1>;
|
||||
};
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||||
@ -75,6 +75,10 @@ properties:
|
||||
- riscv,sv57
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- riscv,none
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||||
|
||||
reg:
|
||||
description:
|
||||
The hart ID of this CPU node.
|
||||
|
||||
riscv,cbom-block-size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
|
||||
@ -8987,6 +8987,11 @@ F: Documentation/i2c/muxes/i2c-mux-gpio.rst
|
||||
F: drivers/i2c/muxes/i2c-mux-gpio.c
|
||||
F: include/linux/platform_data/i2c-mux-gpio.h
|
||||
|
||||
GENERIC GPIO RESET DRIVER
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
S: Maintained
|
||||
F: drivers/reset/reset-gpio.c
|
||||
|
||||
GENERIC HDLC (WAN) DRIVERS
|
||||
M: Krzysztof Halasa <khc@pm.waw.pl>
|
||||
S: Maintained
|
||||
|
||||
@ -108,30 +108,31 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x664>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
|
||||
ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm0_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
|
||||
ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm1_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
|
||||
ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
|
||||
reg = <2>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "ehrpwm2_tbclk";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -566,17 +567,19 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x52c>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
|
||||
gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "gfx_fclk_clksel_ck";
|
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: clock-gfx-fck-div {
|
||||
gfx_fck_div_ck: clock-gfx-fck-div@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "gfx_fck_div_ck";
|
||||
@ -589,30 +592,32 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x700>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sysclkout_pre_ck: clock-sysclkout-pre {
|
||||
sysclkout_pre_ck: clock-sysclkout-pre@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "sysclkout_pre_ck";
|
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
||||
};
|
||||
|
||||
clkout2_div_ck: clock-clkout2-div {
|
||||
clkout2_div_ck: clock-clkout2-div@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "clkout2_div_ck";
|
||||
clocks = <&sysclkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
};
|
||||
|
||||
clkout2_ck: clock-clkout2 {
|
||||
clkout2_ck: clock-clkout2@7 {
|
||||
reg = <7>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "clkout2_ck";
|
||||
clocks = <&clkout2_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -66,22 +66,23 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ipss_ick: clock-ipss-ick {
|
||||
ipss_ick: clock-ipss-ick@4 {
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-interface-clock";
|
||||
clock-output-names = "ipss_ick";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
uart4_ick_am35xx: clock-uart4-ick-am35xx {
|
||||
uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
|
||||
reg = <23>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "uart4_ick_am35xx";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -101,14 +102,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
uart4_fck_am35xx: clock-uart4-fck-am35xx {
|
||||
uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
|
||||
reg = <23>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "uart4_fck_am35xx";
|
||||
clocks = <&core_48m_fck>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -50,30 +50,31 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
d2d_26m_fck: clock-d2d-26m-fck {
|
||||
d2d_26m_fck: clock-d2d-26m-fck@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "d2d_26m_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
fshostusb_fck: clock-fshostusb-fck {
|
||||
fshostusb_fck: clock-fshostusb-fck@5 {
|
||||
reg = <5>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "fshostusb_fck";
|
||||
clocks = <&core_48m_fck>;
|
||||
ti,bit-shift = <5>;
|
||||
};
|
||||
|
||||
ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
|
||||
ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clock-output-names = "ssi_ssr_gate_fck_3430es1";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -81,23 +82,24 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa40>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
|
||||
ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
|
||||
reg = <8>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clock-output-names = "ssi_ssr_div_fck_3430es1";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: clock-usb-l4-div-ick {
|
||||
usb_l4_div_ick: clock-usb-l4-div-ick@4 {
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clock-output-names = "usb_l4_div_ick";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
@ -121,38 +123,39 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
|
||||
hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clock-output-names = "hsotgusb_ick_3430es1";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
fac_ick: clock-fac-ick {
|
||||
fac_ick: clock-fac-ick@8 {
|
||||
reg = <8>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "fac_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
};
|
||||
|
||||
ssi_ick: clock-ssi-ick-3430es1 {
|
||||
ssi_ick: clock-ssi-ick-3430es1@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clock-output-names = "ssi_ick_3430es1";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usb_l4_gate_ick: clock-usb-l4-gate-ick {
|
||||
usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
|
||||
reg = <5>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clock-output-names = "usb_l4_gate_ick";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -174,14 +177,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xe00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "dss1_alwon_fck_3430es1";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
};
|
||||
|
||||
@ -17,46 +17,47 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa14>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
aes1_ick: clock-aes1-ick {
|
||||
aes1_ick: clock-aes1-ick@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "aes1_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
rng_ick: clock-rng-ick {
|
||||
rng_ick: clock-rng-ick@2 {
|
||||
reg = <2>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "rng_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
sha11_ick: clock-sha11-ick {
|
||||
sha11_ick: clock-sha11-ick@1 {
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "sha11_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
des1_ick: clock-des1-ick {
|
||||
des1_ick: clock-des1-ick@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "des1_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
pka_ick: clock-pka-ick {
|
||||
pka_ick: clock-pka-ick@4 {
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "pka_ick";
|
||||
clocks = <&security_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -65,23 +66,24 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xf00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cam_mclk: clock-cam-mclk {
|
||||
cam_mclk: clock-cam-mclk@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "cam_mclk";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
csi2_96m_fck: clock-csi2-96m-fck {
|
||||
csi2_96m_fck: clock-csi2-96m-fck@1 {
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "csi2_96m_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -105,46 +107,47 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icr_ick: clock-icr-ick {
|
||||
icr_ick: clock-icr-ick@29 {
|
||||
reg = <29>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "icr_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
|
||||
des2_ick: clock-des2-ick {
|
||||
des2_ick: clock-des2-ick@26 {
|
||||
reg = <26>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "des2_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
|
||||
mspro_ick: clock-mspro-ick {
|
||||
mspro_ick: clock-mspro-ick@23 {
|
||||
reg = <23>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mspro_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
mailboxes_ick: clock-mailboxes-ick {
|
||||
mailboxes_ick: clock-mailboxes-ick@7 {
|
||||
reg = <7>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mailboxes_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
sad2d_ick: clock-sad2d-ick {
|
||||
sad2d_ick: clock-sad2d-ick@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "sad2d_ick";
|
||||
clocks = <&l3_ick>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -160,22 +163,23 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sr1_fck: clock-sr1-fck {
|
||||
sr1_fck: clock-sr1-fck@6 {
|
||||
reg = <6>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "sr1_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
|
||||
sr2_fck: clock-sr2-fck {
|
||||
sr2_fck: clock-sr2-fck@7 {
|
||||
reg = <7>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "sr2_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -228,22 +232,23 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
modem_fck: clock-modem-fck {
|
||||
modem_fck: clock-modem-fck@31 {
|
||||
reg = <31>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "modem_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <31>;
|
||||
};
|
||||
|
||||
mspro_fck: clock-mspro-fck {
|
||||
mspro_fck: clock-mspro-fck@23 {
|
||||
reg = <23>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "mspro_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -252,14 +257,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa18>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#ssize-cells = <0>;
|
||||
|
||||
mad2d_ick: clock-mad2d-ick {
|
||||
mad2d_ick: clock-mad2d-ick@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mad2d_ick";
|
||||
clocks = <&l3_ick>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -138,14 +138,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa18>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usbtll_ick: clock-usbtll-ick {
|
||||
usbtll_ick: clock-usbtll-ick@2 {
|
||||
reg = <2>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "usbtll_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -153,14 +154,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mmchs3_ick: clock-mmchs3-ick {
|
||||
mmchs3_ick: clock-mmchs3-ick@30 {
|
||||
reg = <30>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mmchs3_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -168,14 +170,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mmchs3_fck: clock-mmchs3-fck {
|
||||
mmchs3_fck: clock-mmchs3-fck@30 {
|
||||
reg = <30>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "mmchs3_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -183,14 +186,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xe00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clock-output-names = "dss1_alwon_fck_3430es2";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
};
|
||||
|
||||
@ -62,14 +62,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x1000>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
uart4_fck: clock-uart4-fck {
|
||||
uart4_fck: clock-uart4-fck@18 {
|
||||
reg = <18>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "uart4_fck";
|
||||
clocks = <&per_48m_fck>;
|
||||
ti,bit-shift = <18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -9,14 +9,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
|
||||
ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clock-output-names = "ssi_ssr_gate_fck_3430es2";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -24,14 +25,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa40>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
|
||||
ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 {
|
||||
reg = <8>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clock-output-names = "ssi_ssr_div_fck_3430es2";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
};
|
||||
@ -54,22 +56,23 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
|
||||
hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 {
|
||||
reg = <4>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clock-output-names = "hsotgusb_ick_3430es2";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
ssi_ick: clock-ssi-ick-3430es2 {
|
||||
ssi_ick: clock-ssi-ick-3430es2@0 {
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clock-output-names = "ssi_ick_3430es2";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -85,14 +88,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usim_gate_fck: clock-usim-gate-fck {
|
||||
usim_gate_fck: clock-usim-gate-fck@9 {
|
||||
reg = <9>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clock-output-names = "usim_gate_fck";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -172,14 +176,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc40>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usim_mux_fck: clock-usim-mux-fck {
|
||||
usim_mux_fck: clock-usim-mux-fck@3 {
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clock-output-names = "usim_mux_fck";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
};
|
||||
@ -194,14 +199,15 @@
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usim_ick: clock-usim-ick {
|
||||
usim_ick: clock-usim-ick@9 {
|
||||
reg = <9>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "usim_ick";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -27,6 +27,7 @@
|
||||
#define UARTA_72165 UARTA_7278
|
||||
#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
|
||||
#define UARTA_7366 UARTA_7364
|
||||
#define UARTA_74165 UARTA_7278
|
||||
#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
|
||||
#define UARTA_7439 REG_PHYS_ADDR(0x40a900)
|
||||
#define UARTA_7445 REG_PHYS_ADDR(0x40ab00)
|
||||
@ -88,9 +89,10 @@ ARM_BE8( rev \rv, \rv )
|
||||
30: checkuart(\rp, \rv, 0x72780000, 7278)
|
||||
31: checkuart(\rp, \rv, 0x73640000, 7364)
|
||||
32: checkuart(\rp, \rv, 0x73660000, 7366)
|
||||
33: checkuart(\rp, \rv, 0x07437100, 74371)
|
||||
34: checkuart(\rp, \rv, 0x74390000, 7439)
|
||||
35: checkuart(\rp, \rv, 0x74450000, 7445)
|
||||
33: checkuart(\rp, \rv, 0x07416500, 74165)
|
||||
34: checkuart(\rp, \rv, 0x07437100, 74371)
|
||||
35: checkuart(\rp, \rv, 0x74390000, 7439)
|
||||
36: checkuart(\rp, \rv, 0x74450000, 7445)
|
||||
|
||||
/* No valid UART found */
|
||||
90: mov \rp, #0
|
||||
|
||||
@ -93,7 +93,6 @@ config ARCH_BCM_MOBILE
|
||||
select ARM_ERRATA_775420
|
||||
select ARM_GIC
|
||||
select GPIO_BCM_KONA
|
||||
select TICK_ONESHOT
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select PINCTRL
|
||||
select ARCH_BCM_MOBILE_SMP if SMP
|
||||
|
||||
@ -185,16 +185,17 @@
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "cferom";
|
||||
reg = <0x0 0x100000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x100000>;
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
base_mac_addr: mac@106a0 {
|
||||
reg = <0x106a0 0x6>;
|
||||
base_mac_addr: mac@106a0 {
|
||||
reg = <0x106a0 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -227,9 +227,6 @@
|
||||
brcm,num-gphy = <5>;
|
||||
brcm,num-rgmii-ports = <2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -243,7 +243,7 @@
|
||||
};
|
||||
|
||||
pdma: dma-controller@3000000 {
|
||||
compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
|
||||
compatible = "microchip,mpfs-pdma", "sifive,pdma0";
|
||||
reg = <0x0 0x3000000 0x0 0x8000>;
|
||||
interrupt-parent = <&plic>;
|
||||
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
|
||||
@ -422,7 +422,7 @@
|
||||
can0: can@2010c000 {
|
||||
compatible = "microchip,mpfs-can";
|
||||
reg = <0x0 0x2010c000 0x0 0x1000>;
|
||||
clocks = <&clkcfg CLK_CAN0>;
|
||||
clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
|
||||
interrupt-parent = <&plic>;
|
||||
interrupts = <56>;
|
||||
status = "disabled";
|
||||
@ -431,7 +431,7 @@
|
||||
can1: can@2010d000 {
|
||||
compatible = "microchip,mpfs-can";
|
||||
reg = <0x0 0x2010d000 0x0 0x1000>;
|
||||
clocks = <&clkcfg CLK_CAN1>;
|
||||
clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
|
||||
interrupt-parent = <&plic>;
|
||||
interrupts = <57>;
|
||||
status = "disabled";
|
||||
|
||||
@ -11,3 +11,14 @@
|
||||
model = "BeagleV Starlight Beta";
|
||||
compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-handle = <&phy>;
|
||||
};
|
||||
|
||||
&mdio {
|
||||
phy: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -72,7 +72,91 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
gmac_pins: gmac-0 {
|
||||
gtxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(115)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <35>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
miitxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(116)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
tx-pins {
|
||||
pins = <PAD_FUNC_SHARE(117)>,
|
||||
<PAD_FUNC_SHARE(119)>,
|
||||
<PAD_FUNC_SHARE(120)>,
|
||||
<PAD_FUNC_SHARE(121)>,
|
||||
<PAD_FUNC_SHARE(122)>,
|
||||
<PAD_FUNC_SHARE(123)>,
|
||||
<PAD_FUNC_SHARE(124)>,
|
||||
<PAD_FUNC_SHARE(125)>,
|
||||
<PAD_FUNC_SHARE(126)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <35>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
rxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(127)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <6>;
|
||||
};
|
||||
rxer-pins {
|
||||
pins = <PAD_FUNC_SHARE(129)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
rx-pins {
|
||||
pins = <PAD_FUNC_SHARE(128)>,
|
||||
<PAD_FUNC_SHARE(130)>,
|
||||
<PAD_FUNC_SHARE(131)>,
|
||||
<PAD_FUNC_SHARE(132)>,
|
||||
<PAD_FUNC_SHARE(133)>,
|
||||
<PAD_FUNC_SHARE(134)>,
|
||||
<PAD_FUNC_SHARE(135)>,
|
||||
<PAD_FUNC_SHARE(136)>,
|
||||
<PAD_FUNC_SHARE(137)>,
|
||||
<PAD_FUNC_SHARE(138)>,
|
||||
<PAD_FUNC_SHARE(139)>,
|
||||
<PAD_FUNC_SHARE(140)>,
|
||||
<PAD_FUNC_SHARE(141)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(62, GPO_LOW,
|
||||
@ -115,6 +199,24 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-0 {
|
||||
pwm-pins {
|
||||
pinmux = <GPIOMUX(7,
|
||||
GPO_PWM_PAD_OUT_BIT0,
|
||||
GPO_PWM_PAD_OE_N_BIT0,
|
||||
GPI_NONE)>,
|
||||
<GPIOMUX(5,
|
||||
GPO_PWM_PAD_OUT_BIT1,
|
||||
GPO_PWM_PAD_OE_N_BIT1,
|
||||
GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <35>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio0_pins: sdio0-0 {
|
||||
clk-pins {
|
||||
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
|
||||
@ -257,6 +359,12 @@
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
|
||||
@ -6,7 +6,6 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7100-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "StarFive VisionFive V1";
|
||||
@ -18,3 +17,24 @@
|
||||
priority = <224>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-handle = <&phy>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
|
||||
* manual adjustment of the RX internal delay to work properly. The default
|
||||
* RX delay provided by the driver (1.95ns) is too high, but applying a 50%
|
||||
* reduction seems to mitigate the issue.
|
||||
*
|
||||
* It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
|
||||
* which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
|
||||
* responsible for the misbehaviour, not the GMAC.
|
||||
*/
|
||||
&mdio {
|
||||
phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
rx-internal-delay-ps = <900>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -208,6 +208,37 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: ethernet@10020000 {
|
||||
compatible = "starfive,jh7100-dwmac", "snps,dwmac";
|
||||
reg = <0x0 0x10020000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
|
||||
<&clkgen JH7100_CLK_GMAC_AHB>,
|
||||
<&clkgen JH7100_CLK_GMAC_PTP_REF>,
|
||||
<&clkgen JH7100_CLK_GMAC_TX_INV>,
|
||||
<&clkgen JH7100_CLK_GMAC_GTX>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
|
||||
resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <6>, <7>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
max-frame-size = <9000>;
|
||||
snps,multicast-filter-bins = <32>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
starfive,syscon = <&sysmain 0x70 0>;
|
||||
rx-fifo-depth = <32768>;
|
||||
tx-fifo-depth = <16384>;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,fixed-burst;
|
||||
snps,force_thresh_dma_mode;
|
||||
status = "disabled";
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <16>;
|
||||
snps,rd_osr_lmt = <16>;
|
||||
snps,blen = <256 128 64 32 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
clkgen: clock-controller@11800000 {
|
||||
compatible = "starfive,jh7100-clkgen";
|
||||
reg = <0x0 0x11800000 0x0 0x10000>;
|
||||
@ -222,6 +253,11 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
sysmain: syscon@11850000 {
|
||||
compatible = "starfive,jh7100-sysmain", "syscon";
|
||||
reg = <0x0 0x11850000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@118b0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x118b0000 0x0 0x10000>;
|
||||
@ -324,6 +360,15 @@
|
||||
<&rstgen JH7100_RSTN_WDT>;
|
||||
};
|
||||
|
||||
pwm: pwm@12490000 {
|
||||
compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
|
||||
reg = <0x0 0x12490000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_PWM_APB>;
|
||||
resets = <&rstgen JH7100_RSTN_PWM_APB>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfctemp: temperature-sensor@124a0000 {
|
||||
compatible = "starfive,jh7100-temp";
|
||||
reg = <0x0 0x124a0000 0x0 0x10000>;
|
||||
|
||||
@ -125,6 +125,55 @@
|
||||
clock-frequency = <49152000>;
|
||||
};
|
||||
|
||||
&camss {
|
||||
assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
||||
<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
|
||||
assigned-clock-rates = <49500000>, <198000000>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
camss_from_csi2rx: endpoint {
|
||||
remote-endpoint = <&csi2rx_to_camss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2rx {
|
||||
assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
|
||||
assigned-clock-rates = <297000000>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
/* remote MIPI sensor endpoint */
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csi2rx_to_camss: endpoint {
|
||||
remote-endpoint = <&camss_from_csi2rx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
@ -323,6 +372,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
@ -513,6 +568,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-0 {
|
||||
pwm-pins {
|
||||
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
|
||||
GPOEN_SYS_PWM0_CHANNEL0,
|
||||
GPI_NONE)>,
|
||||
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
|
||||
GPOEN_SYS_PWM0_CHANNEL1,
|
||||
GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0_pins: spi0-0 {
|
||||
mosi-pins {
|
||||
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
|
||||
|
||||
@ -829,6 +829,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@120d0000 {
|
||||
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
|
||||
reg = <0x0 0x120d0000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
|
||||
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfctemp: temperature-sensor@120e0000 {
|
||||
compatible = "starfive,jh7110-temp";
|
||||
reg = <0x0 0x120e0000 0x0 0x10000>;
|
||||
@ -1104,6 +1113,32 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
csi2rx: csi@19800000 {
|
||||
compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x0 0x19800000 0x0 0x10000>;
|
||||
clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_APB>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
|
||||
clock-names = "sys_clk", "p_clk",
|
||||
"pixel_if0_clk", "pixel_if1_clk",
|
||||
"pixel_if2_clk", "pixel_if3_clk";
|
||||
resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_APB>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
|
||||
reset-names = "sys", "reg_bank",
|
||||
"pixel_if0", "pixel_if1",
|
||||
"pixel_if2", "pixel_if3";
|
||||
phys = <&csi_phy>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ispcrg: clock-controller@19810000 {
|
||||
compatible = "starfive,jh7110-ispcrg";
|
||||
reg = <0x0 0x19810000 0x0 0x10000>;
|
||||
@ -1121,6 +1156,47 @@
|
||||
power-domains = <&pwrc JH7110_PD_ISP>;
|
||||
};
|
||||
|
||||
csi_phy: phy@19820000 {
|
||||
compatible = "starfive,jh7110-dphy-rx";
|
||||
reg = <0x0 0x19820000 0x0 0x10000>;
|
||||
clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
|
||||
<&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
|
||||
<&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
|
||||
clock-names = "cfg", "ref", "tx";
|
||||
resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
|
||||
<&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
|
||||
power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
camss: isp@19840000 {
|
||||
compatible = "starfive,jh7110-camss";
|
||||
reg = <0x0 0x19840000 0x0 0x10000>,
|
||||
<0x0 0x19870000 0x0 0x30000>;
|
||||
reg-names = "syscon", "isp";
|
||||
clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
||||
<&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
|
||||
<&ispcrg JH7110_ISPCLK_DVP_INV>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
|
||||
<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
|
||||
<&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
|
||||
clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
|
||||
"axiwr", "mipi_rx0_pxl", "ispcore_2x",
|
||||
"isp_axi";
|
||||
resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
|
||||
<&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
|
||||
<&syscrg JH7110_SYSRST_ISP_TOP>,
|
||||
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
|
||||
reset-names = "wrapper_p", "wrapper_c", "axird",
|
||||
"axiwr", "isp_top_n", "isp_top_axi";
|
||||
power-domains = <&pwrc JH7110_PD_ISP>;
|
||||
interrupts = <92>, <87>, <90>, <88>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
voutcrg: clock-controller@295c0000 {
|
||||
compatible = "starfive,jh7110-voutcrg";
|
||||
reg = <0x0 0x295c0000 0x0 0x10000>;
|
||||
|
||||
@ -96,6 +96,20 @@ static const int gisb_offsets_bcm7400[] = {
|
||||
[ARB_ERR_CAP_MASTER] = 0x0d8,
|
||||
};
|
||||
|
||||
static const int gisb_offsets_bcm74165[] = {
|
||||
[ARB_TIMER] = 0x008,
|
||||
[ARB_BP_CAP_CLR] = 0x044,
|
||||
[ARB_BP_CAP_HI_ADDR] = -1,
|
||||
[ARB_BP_CAP_ADDR] = 0x048,
|
||||
[ARB_BP_CAP_STATUS] = 0x058,
|
||||
[ARB_BP_CAP_MASTER] = 0x05c,
|
||||
[ARB_ERR_CAP_CLR] = 0x038,
|
||||
[ARB_ERR_CAP_HI_ADDR] = -1,
|
||||
[ARB_ERR_CAP_ADDR] = 0x020,
|
||||
[ARB_ERR_CAP_STATUS] = 0x030,
|
||||
[ARB_ERR_CAP_MASTER] = 0x034,
|
||||
};
|
||||
|
||||
static const int gisb_offsets_bcm7435[] = {
|
||||
[ARB_TIMER] = 0x00c,
|
||||
[ARB_BP_CAP_CLR] = 0x014,
|
||||
@ -393,6 +407,7 @@ static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
|
||||
{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
|
||||
{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
|
||||
{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
|
||||
{ .compatible = "brcm,bcm74165-gisb-arb", .data = gisb_offsets_bcm74165 },
|
||||
{ },
|
||||
};
|
||||
|
||||
|
||||
@ -39,45 +39,39 @@ struct ts_nbus {
|
||||
/*
|
||||
* request all gpios required by the bus.
|
||||
*/
|
||||
static int ts_nbus_init_pdata(struct platform_device *pdev, struct ts_nbus
|
||||
*ts_nbus)
|
||||
static int ts_nbus_init_pdata(struct platform_device *pdev,
|
||||
struct ts_nbus *ts_nbus)
|
||||
{
|
||||
ts_nbus->data = devm_gpiod_get_array(&pdev->dev, "ts,data",
|
||||
GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ts_nbus->data)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,data-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->data);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->data))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->data),
|
||||
"failed to retrieve ts,data-gpio from dts\n");
|
||||
|
||||
ts_nbus->csn = devm_gpiod_get(&pdev->dev, "ts,csn", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ts_nbus->csn)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,csn-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->csn);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->csn))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->csn),
|
||||
"failed to retrieve ts,csn-gpio from dts\n");
|
||||
|
||||
ts_nbus->txrx = devm_gpiod_get(&pdev->dev, "ts,txrx", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ts_nbus->txrx)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,txrx-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->txrx);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->txrx))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->txrx),
|
||||
"failed to retrieve ts,txrx-gpio from dts\n");
|
||||
|
||||
ts_nbus->strobe = devm_gpiod_get(&pdev->dev, "ts,strobe", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ts_nbus->strobe)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,strobe-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->strobe);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->strobe))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->strobe),
|
||||
"failed to retrieve ts,strobe-gpio from dts\n");
|
||||
|
||||
ts_nbus->ale = devm_gpiod_get(&pdev->dev, "ts,ale", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ts_nbus->ale)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,ale-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->ale);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->ale))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->ale),
|
||||
"failed to retrieve ts,ale-gpio from dts\n");
|
||||
|
||||
ts_nbus->rdy = devm_gpiod_get(&pdev->dev, "ts,rdy", GPIOD_IN);
|
||||
if (IS_ERR(ts_nbus->rdy)) {
|
||||
dev_err(&pdev->dev, "failed to retrieve ts,rdy-gpio from dts\n");
|
||||
return PTR_ERR(ts_nbus->rdy);
|
||||
}
|
||||
if (IS_ERR(ts_nbus->rdy))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(ts_nbus->rdy),
|
||||
"failed to retrieve ts,rdy-gpio from dts\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -273,7 +267,7 @@ EXPORT_SYMBOL_GPL(ts_nbus_write);
|
||||
static int ts_nbus_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct pwm_device *pwm;
|
||||
struct pwm_args pargs;
|
||||
struct pwm_state state;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ts_nbus *ts_nbus;
|
||||
int ret;
|
||||
@ -289,32 +283,24 @@ static int ts_nbus_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
|
||||
pwm = devm_pwm_get(dev, NULL);
|
||||
if (IS_ERR(pwm)) {
|
||||
ret = PTR_ERR(pwm);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "unable to request PWM\n");
|
||||
return ret;
|
||||
}
|
||||
if (IS_ERR(pwm))
|
||||
return dev_err_probe(dev, PTR_ERR(pwm),
|
||||
"unable to request PWM\n");
|
||||
|
||||
pwm_get_args(pwm, &pargs);
|
||||
if (!pargs.period) {
|
||||
dev_err(&pdev->dev, "invalid PWM period\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
pwm_init_state(pwm, &state);
|
||||
if (!state.period)
|
||||
return dev_err_probe(dev, -EINVAL, "invalid PWM period\n");
|
||||
|
||||
/*
|
||||
* FIXME: pwm_apply_args() should be removed when switching to
|
||||
* the atomic PWM API.
|
||||
*/
|
||||
pwm_apply_args(pwm);
|
||||
ret = pwm_config(pwm, pargs.period, pargs.period);
|
||||
state.duty_cycle = state.period;
|
||||
state.enabled = true;
|
||||
|
||||
ret = pwm_apply_state(pwm, &state);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return dev_err_probe(dev, ret, "failed to configure PWM\n");
|
||||
|
||||
/*
|
||||
* we can now start the FPGA and populate the peripherals.
|
||||
*/
|
||||
pwm_enable(pwm);
|
||||
ts_nbus->pwm = pwm;
|
||||
|
||||
/*
|
||||
@ -324,7 +310,8 @@ static int ts_nbus_probe(struct platform_device *pdev)
|
||||
|
||||
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return dev_err_probe(dev, ret,
|
||||
"failed to populate platform devices on bus\n");
|
||||
|
||||
dev_info(dev, "initialized\n");
|
||||
|
||||
|
||||
@ -376,14 +376,9 @@ static void __init of_omap2_apll_setup(struct device_node *node)
|
||||
}
|
||||
clk_hw->fixed_rate = val;
|
||||
|
||||
if (of_property_read_u32(node, "ti,bit-shift", &val)) {
|
||||
pr_err("%pOFn missing bit-shift\n", node);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
clk_hw->enable_bit = val;
|
||||
ad->enable_mask = 0x3 << val;
|
||||
ad->autoidle_mask = 0x3 << val;
|
||||
clk_hw->enable_bit = ti_clk_get_legacy_bit_shift(node);
|
||||
ad->enable_mask = 0x3 << clk_hw->enable_bit;
|
||||
ad->autoidle_mask = 0x3 << clk_hw->enable_bit;
|
||||
|
||||
if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
|
||||
pr_err("%pOFn missing idlest-shift\n", node);
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*/
|
||||
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
@ -15,6 +16,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/minmax.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/string_helpers.h>
|
||||
#include <linux/memblock.h>
|
||||
@ -114,20 +116,26 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
|
||||
|
||||
/*
|
||||
* Eventually we could standardize to using '_' for clk-*.c files to follow the
|
||||
* TRM naming and leave out the tmp name here.
|
||||
* TRM naming.
|
||||
*/
|
||||
static struct device_node *ti_find_clock_provider(struct device_node *from,
|
||||
const char *name)
|
||||
{
|
||||
char *tmp __free(kfree) = NULL;
|
||||
struct device_node *np;
|
||||
bool found = false;
|
||||
const char *n;
|
||||
char *tmp;
|
||||
char *p;
|
||||
|
||||
tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL);
|
||||
if (!tmp)
|
||||
return NULL;
|
||||
|
||||
/* Ignore a possible address for the node name */
|
||||
p = strchr(tmp, '@');
|
||||
if (p)
|
||||
*p = '\0';
|
||||
|
||||
/* Node named "clock" with "clock-output-names" */
|
||||
for_each_of_allnodes_from(from, np) {
|
||||
if (of_property_read_string_index(np, "clock-output-names",
|
||||
@ -140,7 +148,6 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
|
||||
break;
|
||||
}
|
||||
}
|
||||
kfree(tmp);
|
||||
|
||||
if (found) {
|
||||
of_node_put(from);
|
||||
@ -148,7 +155,7 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
|
||||
}
|
||||
|
||||
/* Fall back to using old node name base provider name */
|
||||
return of_find_node_by_name(from, name);
|
||||
return of_find_node_by_name(from, tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -301,8 +308,9 @@ int __init ti_clk_retry_init(struct device_node *node, void *user,
|
||||
int ti_clk_get_reg_addr(struct device_node *node, int index,
|
||||
struct clk_omap_reg *reg)
|
||||
{
|
||||
u32 val;
|
||||
int i;
|
||||
u32 clksel_addr, val;
|
||||
bool is_clksel = false;
|
||||
int i, err;
|
||||
|
||||
for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
|
||||
if (clocks_node_ptr[i] == node->parent)
|
||||
@ -318,21 +326,62 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
|
||||
|
||||
reg->index = i;
|
||||
|
||||
if (of_property_read_u32_index(node, "reg", index, &val)) {
|
||||
if (of_property_read_u32_index(node->parent, "reg",
|
||||
index, &val)) {
|
||||
pr_err("%pOFn or parent must have reg[%d]!\n",
|
||||
node, index);
|
||||
if (of_device_is_compatible(node->parent, "ti,clksel")) {
|
||||
err = of_property_read_u32_index(node->parent, "reg", index, &clksel_addr);
|
||||
if (err) {
|
||||
pr_err("%pOFn parent clksel must have reg[%d]!\n", node, index);
|
||||
return -EINVAL;
|
||||
}
|
||||
is_clksel = true;
|
||||
}
|
||||
|
||||
err = of_property_read_u32_index(node, "reg", index, &val);
|
||||
if (err && is_clksel) {
|
||||
/* Legacy clksel with no reg and a possible ti,bit-shift property */
|
||||
reg->offset = clksel_addr;
|
||||
reg->bit = ti_clk_get_legacy_bit_shift(node);
|
||||
reg->ptr = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Updated clksel clock with a proper reg property */
|
||||
if (is_clksel) {
|
||||
reg->offset = clksel_addr;
|
||||
reg->bit = val;
|
||||
reg->ptr = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Other clocks that may or may not have ti,bit-shift property */
|
||||
reg->offset = val;
|
||||
reg->bit = ti_clk_get_legacy_bit_shift(node);
|
||||
reg->ptr = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_clk_get_legacy_bit_shift - get bit shift for a clock register
|
||||
* @node: device node for the clock
|
||||
*
|
||||
* Gets the clock register bit shift using the legacy ti,bit-shift
|
||||
* property. Only needed for legacy clock, and can be eventually
|
||||
* dropped once all the composite clocks use a clksel node with a
|
||||
* proper reg property.
|
||||
*/
|
||||
int ti_clk_get_legacy_bit_shift(struct device_node *node)
|
||||
{
|
||||
int err;
|
||||
u32 val;
|
||||
|
||||
err = of_property_read_u32(node, "ti,bit-shift", &val);
|
||||
if (!err && in_range(val, 0, 32))
|
||||
return val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
|
||||
{
|
||||
u32 latch;
|
||||
|
||||
@ -216,6 +216,7 @@ int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
|
||||
|
||||
int ti_clk_get_reg_addr(struct device_node *node, int index,
|
||||
struct clk_omap_reg *reg);
|
||||
int ti_clk_get_legacy_bit_shift(struct device_node *node);
|
||||
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
|
||||
int ti_clk_retry_init(struct device_node *node, void *user,
|
||||
ti_of_clk_init_cb_t func);
|
||||
|
||||
@ -477,10 +477,7 @@ static int __init ti_clk_divider_populate(struct device_node *node,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
div->shift = val;
|
||||
else
|
||||
div->shift = 0;
|
||||
div->shift = div->reg.bit;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,latch-bit", &val))
|
||||
div->latch = val;
|
||||
|
||||
@ -132,7 +132,6 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
struct clk_omap_reg reg;
|
||||
const char *name;
|
||||
u8 enable_bit = 0;
|
||||
u32 val;
|
||||
u32 flags = 0;
|
||||
u8 clk_gate_flags = 0;
|
||||
|
||||
@ -140,8 +139,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
if (ti_clk_get_reg_addr(node, 0, ®))
|
||||
return;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
enable_bit = val;
|
||||
enable_bit = reg.bit;
|
||||
}
|
||||
|
||||
if (of_clk_get_parent_count(node) != 1) {
|
||||
@ -170,7 +168,6 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk_hw_omap *gate;
|
||||
u32 val = 0;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
@ -179,9 +176,7 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
|
||||
if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
|
||||
goto cleanup;
|
||||
|
||||
of_property_read_u32(node, "ti,bit-shift", &val);
|
||||
|
||||
gate->enable_bit = val;
|
||||
gate->enable_bit = gate->enable_reg.bit;
|
||||
gate->ops = hw_ops;
|
||||
|
||||
if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
|
||||
|
||||
@ -66,13 +66,11 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
struct clk_omap_reg reg;
|
||||
u8 enable_bit = 0;
|
||||
const char *name;
|
||||
u32 val;
|
||||
|
||||
if (ti_clk_get_reg_addr(node, 0, ®))
|
||||
return;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
enable_bit = val;
|
||||
enable_bit = reg.bit;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
|
||||
@ -189,7 +189,7 @@ static void of_mux_clk_setup(struct device_node *node)
|
||||
if (ti_clk_get_reg_addr(node, 0, ®))
|
||||
goto cleanup;
|
||||
|
||||
of_property_read_u32(node, "ti,bit-shift", &shift);
|
||||
shift = reg.bit;
|
||||
|
||||
of_property_read_u32(node, "ti,latch-bit", &latch);
|
||||
|
||||
@ -252,7 +252,6 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk_omap_mux *mux;
|
||||
unsigned int num_parents;
|
||||
u32 val;
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
@ -261,8 +260,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
|
||||
if (ti_clk_get_reg_addr(node, 0, &mux->reg))
|
||||
goto cleanup;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
mux->shift = val;
|
||||
mux->shift = mux->reg.bit;
|
||||
|
||||
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
||||
mux->flags |= CLK_MUX_INDEX_ONE;
|
||||
|
||||
@ -66,6 +66,15 @@ config RESET_BRCMSTB_RESCAL
|
||||
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
|
||||
BCM7216.
|
||||
|
||||
config RESET_GPIO
|
||||
tristate "GPIO reset controller"
|
||||
help
|
||||
This enables a generic reset controller for resets attached via
|
||||
GPIOs. Typically for OF platforms this driver expects "reset-gpios"
|
||||
property.
|
||||
|
||||
If compiled as module, it will be called reset-gpio.
|
||||
|
||||
config RESET_HSDK
|
||||
bool "Synopsys HSDK Reset Driver"
|
||||
depends on HAS_IOMEM
|
||||
@ -213,7 +222,7 @@ config RESET_SCMI
|
||||
|
||||
config RESET_SIMPLE
|
||||
bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
|
||||
default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
|
||||
default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
This enables a simple reset controller driver for reset lines that
|
||||
@ -228,6 +237,7 @@ config RESET_SIMPLE
|
||||
- RCC reset controller in STM32 MCUs
|
||||
- Allwinner SoCs
|
||||
- SiFive FU740 SoCs
|
||||
- Sophgo SoCs
|
||||
|
||||
config RESET_SOCFPGA
|
||||
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
|
||||
|
||||
@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
||||
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
|
||||
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
|
||||
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
|
||||
obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
|
||||
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
||||
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
|
||||
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
|
||||
|
||||
@ -5,14 +5,19 @@
|
||||
* Copyright 2013 Philipp Zabel, Pengutronix
|
||||
*/
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/kref.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/idr.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
@ -23,6 +28,11 @@ static LIST_HEAD(reset_controller_list);
|
||||
static DEFINE_MUTEX(reset_lookup_mutex);
|
||||
static LIST_HEAD(reset_lookup_list);
|
||||
|
||||
/* Protects reset_gpio_lookup_list */
|
||||
static DEFINE_MUTEX(reset_gpio_lookup_mutex);
|
||||
static LIST_HEAD(reset_gpio_lookup_list);
|
||||
static DEFINE_IDA(reset_gpio_ida);
|
||||
|
||||
/**
|
||||
* struct reset_control - a reset control
|
||||
* @rcdev: a pointer to the reset controller device
|
||||
@ -63,6 +73,16 @@ struct reset_control_array {
|
||||
struct reset_control *rstc[] __counted_by(num_rstcs);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct reset_gpio_lookup - lookup key for ad-hoc created reset-gpio devices
|
||||
* @of_args: phandle to the reset controller with all the args like GPIO number
|
||||
* @list: list entry for the reset_gpio_lookup_list
|
||||
*/
|
||||
struct reset_gpio_lookup {
|
||||
struct of_phandle_args of_args;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
static const char *rcdev_name(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
if (rcdev->dev)
|
||||
@ -71,6 +91,9 @@ static const char *rcdev_name(struct reset_controller_dev *rcdev)
|
||||
if (rcdev->of_node)
|
||||
return rcdev->of_node->full_name;
|
||||
|
||||
if (rcdev->of_args)
|
||||
return rcdev->of_args->np->full_name;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -99,6 +122,9 @@ static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
|
||||
*/
|
||||
int reset_controller_register(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
if (rcdev->of_node && rcdev->of_args)
|
||||
return -EINVAL;
|
||||
|
||||
if (!rcdev->of_xlate) {
|
||||
rcdev->of_reset_n_cells = 1;
|
||||
rcdev->of_xlate = of_reset_simple_xlate;
|
||||
@ -813,12 +839,171 @@ static void __reset_control_put_internal(struct reset_control *rstc)
|
||||
kref_put(&rstc->refcnt, __reset_control_release);
|
||||
}
|
||||
|
||||
static int __reset_add_reset_gpio_lookup(int id, struct device_node *np,
|
||||
unsigned int gpio,
|
||||
unsigned int of_flags)
|
||||
{
|
||||
const struct fwnode_handle *fwnode = of_fwnode_handle(np);
|
||||
unsigned int lookup_flags;
|
||||
const char *label_tmp;
|
||||
|
||||
/*
|
||||
* Later we map GPIO flags between OF and Linux, however not all
|
||||
* constants from include/dt-bindings/gpio/gpio.h and
|
||||
* include/linux/gpio/machine.h match each other.
|
||||
*/
|
||||
if (of_flags > GPIO_ACTIVE_LOW) {
|
||||
pr_err("reset-gpio code does not support GPIO flags %u for GPIO %u\n",
|
||||
of_flags, gpio);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
struct gpio_device *gdev __free(gpio_device_put) = gpio_device_find_by_fwnode(fwnode);
|
||||
if (!gdev)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
label_tmp = gpio_device_get_label(gdev);
|
||||
if (!label_tmp)
|
||||
return -EINVAL;
|
||||
|
||||
char *label __free(kfree) = kstrdup(label_tmp, GFP_KERNEL);
|
||||
if (!label)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Size: one lookup entry plus sentinel */
|
||||
struct gpiod_lookup_table *lookup __free(kfree) = kzalloc(struct_size(lookup, table, 2),
|
||||
GFP_KERNEL);
|
||||
if (!lookup)
|
||||
return -ENOMEM;
|
||||
|
||||
lookup->dev_id = kasprintf(GFP_KERNEL, "reset-gpio.%d", id);
|
||||
if (!lookup->dev_id)
|
||||
return -ENOMEM;
|
||||
|
||||
lookup_flags = GPIO_PERSISTENT;
|
||||
lookup_flags |= of_flags & GPIO_ACTIVE_LOW;
|
||||
lookup->table[0] = GPIO_LOOKUP(no_free_ptr(label), gpio, "reset",
|
||||
lookup_flags);
|
||||
|
||||
/* Not freed on success, because it is persisent subsystem data. */
|
||||
gpiod_add_lookup_table(no_free_ptr(lookup));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* @args: phandle to the GPIO provider with all the args like GPIO number
|
||||
*/
|
||||
static int __reset_add_reset_gpio_device(const struct of_phandle_args *args)
|
||||
{
|
||||
struct reset_gpio_lookup *rgpio_dev;
|
||||
struct platform_device *pdev;
|
||||
int id, ret;
|
||||
|
||||
/*
|
||||
* Currently only #gpio-cells=2 is supported with the meaning of:
|
||||
* args[0]: GPIO number
|
||||
* args[1]: GPIO flags
|
||||
* TODO: Handle other cases.
|
||||
*/
|
||||
if (args->args_count != 2)
|
||||
return -ENOENT;
|
||||
|
||||
/*
|
||||
* Registering reset-gpio device might cause immediate
|
||||
* bind, resulting in its probe() registering new reset controller thus
|
||||
* taking reset_list_mutex lock via reset_controller_register().
|
||||
*/
|
||||
lockdep_assert_not_held(&reset_list_mutex);
|
||||
|
||||
mutex_lock(&reset_gpio_lookup_mutex);
|
||||
|
||||
list_for_each_entry(rgpio_dev, &reset_gpio_lookup_list, list) {
|
||||
if (args->np == rgpio_dev->of_args.np) {
|
||||
if (of_phandle_args_equal(args, &rgpio_dev->of_args))
|
||||
goto out; /* Already on the list, done */
|
||||
}
|
||||
}
|
||||
|
||||
id = ida_alloc(&reset_gpio_ida, GFP_KERNEL);
|
||||
if (id < 0) {
|
||||
ret = id;
|
||||
goto err_unlock;
|
||||
}
|
||||
|
||||
/* Not freed on success, because it is persisent subsystem data. */
|
||||
rgpio_dev = kzalloc(sizeof(*rgpio_dev), GFP_KERNEL);
|
||||
if (!rgpio_dev) {
|
||||
ret = -ENOMEM;
|
||||
goto err_ida_free;
|
||||
}
|
||||
|
||||
ret = __reset_add_reset_gpio_lookup(id, args->np, args->args[0],
|
||||
args->args[1]);
|
||||
if (ret < 0)
|
||||
goto err_kfree;
|
||||
|
||||
rgpio_dev->of_args = *args;
|
||||
/*
|
||||
* We keep the device_node reference, but of_args.np is put at the end
|
||||
* of __of_reset_control_get(), so get it one more time.
|
||||
* Hold reference as long as rgpio_dev memory is valid.
|
||||
*/
|
||||
of_node_get(rgpio_dev->of_args.np);
|
||||
pdev = platform_device_register_data(NULL, "reset-gpio", id,
|
||||
&rgpio_dev->of_args,
|
||||
sizeof(rgpio_dev->of_args));
|
||||
ret = PTR_ERR_OR_ZERO(pdev);
|
||||
if (ret)
|
||||
goto err_put;
|
||||
|
||||
list_add(&rgpio_dev->list, &reset_gpio_lookup_list);
|
||||
|
||||
out:
|
||||
mutex_unlock(&reset_gpio_lookup_mutex);
|
||||
|
||||
return 0;
|
||||
|
||||
err_put:
|
||||
of_node_put(rgpio_dev->of_args.np);
|
||||
err_kfree:
|
||||
kfree(rgpio_dev);
|
||||
err_ida_free:
|
||||
ida_free(&reset_gpio_ida, id);
|
||||
err_unlock:
|
||||
mutex_unlock(&reset_gpio_lookup_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct reset_controller_dev *__reset_find_rcdev(const struct of_phandle_args *args,
|
||||
bool gpio_fallback)
|
||||
{
|
||||
struct reset_controller_dev *rcdev;
|
||||
|
||||
lockdep_assert_held(&reset_list_mutex);
|
||||
|
||||
list_for_each_entry(rcdev, &reset_controller_list, list) {
|
||||
if (gpio_fallback) {
|
||||
if (rcdev->of_args && of_phandle_args_equal(args,
|
||||
rcdev->of_args))
|
||||
return rcdev;
|
||||
} else {
|
||||
if (args->np == rcdev->of_node)
|
||||
return rcdev;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct reset_control *
|
||||
__of_reset_control_get(struct device_node *node, const char *id, int index,
|
||||
bool shared, bool optional, bool acquired)
|
||||
{
|
||||
bool gpio_fallback = false;
|
||||
struct reset_control *rstc;
|
||||
struct reset_controller_dev *r, *rcdev;
|
||||
struct reset_controller_dev *rcdev;
|
||||
struct of_phandle_args args;
|
||||
int rstc_id;
|
||||
int ret;
|
||||
@ -839,39 +1024,52 @@ __of_reset_control_get(struct device_node *node, const char *id, int index,
|
||||
index, &args);
|
||||
if (ret == -EINVAL)
|
||||
return ERR_PTR(ret);
|
||||
if (ret)
|
||||
return optional ? NULL : ERR_PTR(ret);
|
||||
if (ret) {
|
||||
if (!IS_ENABLED(CONFIG_RESET_GPIO))
|
||||
return optional ? NULL : ERR_PTR(ret);
|
||||
|
||||
mutex_lock(&reset_list_mutex);
|
||||
rcdev = NULL;
|
||||
list_for_each_entry(r, &reset_controller_list, list) {
|
||||
if (args.np == r->of_node) {
|
||||
rcdev = r;
|
||||
break;
|
||||
/*
|
||||
* There can be only one reset-gpio for regular devices, so
|
||||
* don't bother with the "reset-gpios" phandle index.
|
||||
*/
|
||||
ret = of_parse_phandle_with_args(node, "reset-gpios", "#gpio-cells",
|
||||
0, &args);
|
||||
if (ret)
|
||||
return optional ? NULL : ERR_PTR(ret);
|
||||
|
||||
gpio_fallback = true;
|
||||
|
||||
ret = __reset_add_reset_gpio_device(&args);
|
||||
if (ret) {
|
||||
rstc = ERR_PTR(ret);
|
||||
goto out_put;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_lock(&reset_list_mutex);
|
||||
rcdev = __reset_find_rcdev(&args, gpio_fallback);
|
||||
if (!rcdev) {
|
||||
rstc = ERR_PTR(-EPROBE_DEFER);
|
||||
goto out;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
if (WARN_ON(args.args_count != rcdev->of_reset_n_cells)) {
|
||||
rstc = ERR_PTR(-EINVAL);
|
||||
goto out;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
rstc_id = rcdev->of_xlate(rcdev, &args);
|
||||
if (rstc_id < 0) {
|
||||
rstc = ERR_PTR(rstc_id);
|
||||
goto out;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
/* reset_list_mutex also protects the rcdev's reset_control list */
|
||||
rstc = __reset_control_get_internal(rcdev, rstc_id, shared, acquired);
|
||||
|
||||
out:
|
||||
out_unlock:
|
||||
mutex_unlock(&reset_list_mutex);
|
||||
out_put:
|
||||
of_node_put(args.np);
|
||||
|
||||
return rstc;
|
||||
|
||||
119
drivers/reset/reset-gpio.c
Normal file
119
drivers/reset/reset-gpio.c
Normal file
@ -0,0 +1,119 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
struct reset_gpio_priv {
|
||||
struct reset_controller_dev rc;
|
||||
struct gpio_desc *reset;
|
||||
};
|
||||
|
||||
static inline struct reset_gpio_priv
|
||||
*rc_to_reset_gpio(struct reset_controller_dev *rc)
|
||||
{
|
||||
return container_of(rc, struct reset_gpio_priv, rc);
|
||||
}
|
||||
|
||||
static int reset_gpio_assert(struct reset_controller_dev *rc, unsigned long id)
|
||||
{
|
||||
struct reset_gpio_priv *priv = rc_to_reset_gpio(rc);
|
||||
|
||||
gpiod_set_value_cansleep(priv->reset, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int reset_gpio_deassert(struct reset_controller_dev *rc,
|
||||
unsigned long id)
|
||||
{
|
||||
struct reset_gpio_priv *priv = rc_to_reset_gpio(rc);
|
||||
|
||||
gpiod_set_value_cansleep(priv->reset, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int reset_gpio_status(struct reset_controller_dev *rc, unsigned long id)
|
||||
{
|
||||
struct reset_gpio_priv *priv = rc_to_reset_gpio(rc);
|
||||
|
||||
return gpiod_get_value_cansleep(priv->reset);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops reset_gpio_ops = {
|
||||
.assert = reset_gpio_assert,
|
||||
.deassert = reset_gpio_deassert,
|
||||
.status = reset_gpio_status,
|
||||
};
|
||||
|
||||
static int reset_gpio_of_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
return reset_spec->args[0];
|
||||
}
|
||||
|
||||
static void reset_gpio_of_node_put(void *data)
|
||||
{
|
||||
of_node_put(data);
|
||||
}
|
||||
|
||||
static int reset_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct of_phandle_args *platdata = dev_get_platdata(dev);
|
||||
struct reset_gpio_priv *priv;
|
||||
int ret;
|
||||
|
||||
if (!platdata)
|
||||
return -EINVAL;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, &priv->rc);
|
||||
|
||||
priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(priv->reset))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->reset),
|
||||
"Could not get reset gpios\n");
|
||||
|
||||
priv->rc.ops = &reset_gpio_ops;
|
||||
priv->rc.owner = THIS_MODULE;
|
||||
priv->rc.dev = dev;
|
||||
priv->rc.of_args = platdata;
|
||||
ret = devm_add_action_or_reset(dev, reset_gpio_of_node_put,
|
||||
priv->rc.of_node);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Cells to match GPIO specifier, but it's not really used */
|
||||
priv->rc.of_reset_n_cells = 2;
|
||||
priv->rc.of_xlate = reset_gpio_of_xlate;
|
||||
priv->rc.nr_resets = 1;
|
||||
|
||||
return devm_reset_controller_register(dev, &priv->rc);
|
||||
}
|
||||
|
||||
static const struct platform_device_id reset_gpio_ids[] = {
|
||||
{ .name = "reset-gpio", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, reset_gpio_ids);
|
||||
|
||||
static struct platform_driver reset_gpio_driver = {
|
||||
.probe = reset_gpio_probe,
|
||||
.id_table = reset_gpio_ids,
|
||||
.driver = {
|
||||
.name = "reset-gpio",
|
||||
},
|
||||
};
|
||||
module_platform_driver(reset_gpio_driver);
|
||||
|
||||
MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
|
||||
MODULE_DESCRIPTION("Generic GPIO reset driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
|
||||
{ .compatible = "snps,dw-high-reset" },
|
||||
{ .compatible = "snps,dw-low-reset",
|
||||
.data = &reset_simple_active_low },
|
||||
{ .compatible = "sophgo,sg2042-reset",
|
||||
.data = &reset_simple_active_low },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
|
||||
@ -523,7 +523,7 @@ int dpaa2_io_service_enqueue_multiple_desc_fq(struct dpaa2_io *d,
|
||||
struct qbman_eq_desc *ed;
|
||||
int i, ret;
|
||||
|
||||
ed = kcalloc(sizeof(struct qbman_eq_desc), 32, GFP_KERNEL);
|
||||
ed = kcalloc(32, sizeof(struct qbman_eq_desc), GFP_KERNEL);
|
||||
if (!ed)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
87
include/dt-bindings/reset/sophgo,sg2042-reset.h
Normal file
87
include/dt-bindings/reset/sophgo,sg2042-reset.h
Normal file
@ -0,0 +1,87 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
|
||||
#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
|
||||
|
||||
#define RST_MAIN_AP 0
|
||||
#define RST_RISCV_CPU 1
|
||||
#define RST_RISCV_LOW_SPEED_LOGIC 2
|
||||
#define RST_RISCV_CMN 3
|
||||
#define RST_HSDMA 4
|
||||
#define RST_SYSDMA 5
|
||||
#define RST_EFUSE0 6
|
||||
#define RST_EFUSE1 7
|
||||
#define RST_RTC 8
|
||||
#define RST_TIMER 9
|
||||
#define RST_WDT 10
|
||||
#define RST_AHB_ROM0 11
|
||||
#define RST_AHB_ROM1 12
|
||||
#define RST_I2C0 13
|
||||
#define RST_I2C1 14
|
||||
#define RST_I2C2 15
|
||||
#define RST_I2C3 16
|
||||
#define RST_GPIO0 17
|
||||
#define RST_GPIO1 18
|
||||
#define RST_GPIO2 19
|
||||
#define RST_PWM 20
|
||||
#define RST_AXI_SRAM0 21
|
||||
#define RST_AXI_SRAM1 22
|
||||
#define RST_SF0 23
|
||||
#define RST_SF1 24
|
||||
#define RST_LPC 25
|
||||
#define RST_ETH0 26
|
||||
#define RST_EMMC 27
|
||||
#define RST_SD 28
|
||||
#define RST_UART0 29
|
||||
#define RST_UART1 30
|
||||
#define RST_UART2 31
|
||||
#define RST_UART3 32
|
||||
#define RST_SPI0 33
|
||||
#define RST_SPI1 34
|
||||
#define RST_DBG_I2C 35
|
||||
#define RST_PCIE0 36
|
||||
#define RST_PCIE1 37
|
||||
#define RST_DDR0 38
|
||||
#define RST_DDR1 39
|
||||
#define RST_DDR2 40
|
||||
#define RST_DDR3 41
|
||||
#define RST_FAU0 42
|
||||
#define RST_FAU1 43
|
||||
#define RST_FAU2 44
|
||||
#define RST_RXU0 45
|
||||
#define RST_RXU1 46
|
||||
#define RST_RXU2 47
|
||||
#define RST_RXU3 48
|
||||
#define RST_RXU4 49
|
||||
#define RST_RXU5 50
|
||||
#define RST_RXU6 51
|
||||
#define RST_RXU7 52
|
||||
#define RST_RXU8 53
|
||||
#define RST_RXU9 54
|
||||
#define RST_RXU10 55
|
||||
#define RST_RXU11 56
|
||||
#define RST_RXU12 57
|
||||
#define RST_RXU13 58
|
||||
#define RST_RXU14 59
|
||||
#define RST_RXU15 60
|
||||
#define RST_RXU16 61
|
||||
#define RST_RXU17 62
|
||||
#define RST_RXU18 63
|
||||
#define RST_RXU19 64
|
||||
#define RST_RXU20 65
|
||||
#define RST_RXU21 66
|
||||
#define RST_RXU22 67
|
||||
#define RST_RXU23 68
|
||||
#define RST_RXU24 69
|
||||
#define RST_RXU25 70
|
||||
#define RST_RXU26 71
|
||||
#define RST_RXU27 72
|
||||
#define RST_RXU28 73
|
||||
#define RST_RXU29 74
|
||||
#define RST_RXU30 75
|
||||
#define RST_RXU31 76
|
||||
|
||||
#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */
|
||||
@ -13,11 +13,14 @@
|
||||
/**
|
||||
* struct clk_omap_reg - OMAP register declaration
|
||||
* @offset: offset from the master IP module base address
|
||||
* @bit: register bit offset
|
||||
* @index: index of the master IP module
|
||||
* @flags: flags
|
||||
*/
|
||||
struct clk_omap_reg {
|
||||
void __iomem *ptr;
|
||||
u16 offset;
|
||||
u8 bit;
|
||||
u8 index;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
@ -1141,8 +1141,7 @@ static inline int of_perf_domain_get_sharing_cpumask(int pcpu, const char *list_
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
if (pargs->np == args.np && pargs->args_count == args.args_count &&
|
||||
!memcmp(pargs->args, args.args, sizeof(args.args[0]) * args.args_count))
|
||||
if (of_phandle_args_equal(pargs, &args))
|
||||
cpumask_set_cpu(cpu, cpumask);
|
||||
|
||||
of_node_put(args.np);
|
||||
|
||||
@ -1083,6 +1083,22 @@ static inline int of_parse_phandle_with_optional_args(const struct device_node *
|
||||
0, index, out_args);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_phandle_args_equal() - Compare two of_phandle_args
|
||||
* @a1: First of_phandle_args to compare
|
||||
* @a2: Second of_phandle_args to compare
|
||||
*
|
||||
* Return: True if a1 and a2 are the same (same node pointer, same phandle
|
||||
* args), false otherwise.
|
||||
*/
|
||||
static inline bool of_phandle_args_equal(const struct of_phandle_args *a1,
|
||||
const struct of_phandle_args *a2)
|
||||
{
|
||||
return a1->np == a2->np &&
|
||||
a1->args_count == a2->args_count &&
|
||||
!memcmp(a1->args, a2->args, sizeof(a1->args[0]) * a1->args_count);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_property_count_u8_elems - Count the number of u8 elements in a property
|
||||
*
|
||||
|
||||
@ -60,6 +60,9 @@ struct reset_control_lookup {
|
||||
* @reset_control_head: head of internal list of requested reset controls
|
||||
* @dev: corresponding driver model device struct
|
||||
* @of_node: corresponding device tree node as phandle target
|
||||
* @of_args: for reset-gpios controllers: corresponding phandle args with
|
||||
* of_node and GPIO number complementing of_node; either this or
|
||||
* of_node should be present
|
||||
* @of_reset_n_cells: number of cells in reset line specifiers
|
||||
* @of_xlate: translation function to translate from specifier as found in the
|
||||
* device tree to id as given to the reset control ops, defaults
|
||||
@ -73,6 +76,7 @@ struct reset_controller_dev {
|
||||
struct list_head reset_control_head;
|
||||
struct device *dev;
|
||||
struct device_node *of_node;
|
||||
const struct of_phandle_args *of_args;
|
||||
int of_reset_n_cells;
|
||||
int (*of_xlate)(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user