ie31200_edac: Allocate mci and map mchbar first
Check for memory allocation and mchbar mapping failures before initializing the dimm info tables needlessly. Signed-off-by: Jason Baron <jbaron@akamai.com> Suggested-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/ead8f53e699f1ce21c2e17f3cffb4685d4faf72a.1404939455.git.jbaron@akamai.com Signed-off-by: Borislav Petkov <bp@suse.de>
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7ee40b897d
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@ -328,8 +328,7 @@ static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
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static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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{
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{
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int rc;
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int i, j, ret;
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int i, j;
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struct mem_ctl_info *mci = NULL;
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struct mem_ctl_info *mci = NULL;
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struct edac_mc_layer layers[2];
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struct edac_mc_layer layers[2];
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struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
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struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
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@ -344,9 +343,37 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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return -ENODEV;
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return -ENODEV;
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}
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}
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nr_channels = how_many_channels(pdev);
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = IE31200_DIMMS;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = nr_channels;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct ie31200_priv));
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if (!mci)
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return -ENOMEM;
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window = ie31200_map_mchbar(pdev);
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window = ie31200_map_mchbar(pdev);
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if (!window)
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if (!window) {
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return -ENODEV;
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ret = -ENODEV;
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goto fail_free;
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}
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edac_dbg(3, "MC: init mci\n");
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mci->pdev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = IE31200_REVISION;
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mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
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mci->dev_name = pci_name(pdev);
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mci->edac_check = ie31200_check;
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mci->ctl_page_to_phys = NULL;
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priv = mci->pvt_info;
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priv->window = window;
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/* populate DIMM info */
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/* populate DIMM info */
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for (i = 0; i < IE31200_CHANNELS; i++) {
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for (i = 0; i < IE31200_CHANNELS; i++) {
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@ -367,38 +394,6 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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}
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}
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}
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}
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nr_channels = how_many_channels(pdev);
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = IE31200_DIMMS;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = nr_channels;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct ie31200_priv));
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rc = -ENOMEM;
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if (!mci)
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goto fail_unmap;
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edac_dbg(3, "MC: init mci\n");
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mci->pdev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = IE31200_REVISION;
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mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
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mci->dev_name = pci_name(pdev);
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mci->edac_check = ie31200_check;
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mci->ctl_page_to_phys = NULL;
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priv = mci->pvt_info;
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priv->window = window;
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/*
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/*
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* The dram rank boundary (DRB) reg values are boundary addresses
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* The dram rank boundary (DRB) reg values are boundary addresses
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* for each DRAM rank with a granularity of 64MB. DRB regs are
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* for each DRAM rank with a granularity of 64MB. DRB regs are
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@ -439,23 +434,23 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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ie31200_clear_error_info(mci);
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ie31200_clear_error_info(mci);
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rc = -ENODEV;
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if (edac_mc_add_mc(mci)) {
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if (edac_mc_add_mc(mci)) {
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edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
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edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
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goto fail_free;
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ret = -ENODEV;
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goto fail_unmap;
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}
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}
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/* get this far and it's successful */
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/* get this far and it's successful */
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edac_dbg(3, "MC: success\n");
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edac_dbg(3, "MC: success\n");
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return 0;
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return 0;
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fail_free:
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if (mci)
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edac_mc_free(mci);
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fail_unmap:
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fail_unmap:
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iounmap(window);
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iounmap(window);
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return rc;
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fail_free:
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edac_mc_free(mci);
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return ret;
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}
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}
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static int ie31200_init_one(struct pci_dev *pdev,
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static int ie31200_init_one(struct pci_dev *pdev,
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