cxl: Add support for _DSM Function for retrieving QTG ID
CXL spec v3.0 9.17.3 CXL Root Device Specific Methods (_DSM) Add support to retrieve QTG ID via ACPI _DSM call. The _DSM call requires an input of an ACPI package with 4 dwords (read latency, write latency, read bandwidth, write bandwidth). The call returns a package with 1 WORD that provides the max supported QTG ID and a package that may contain 0 or more WORDs as the recommended QTG IDs in the recommended order. Create a cxl_root container for the root cxl_port and provide a callback ->get_qos_class() in order to retrieve the QoS class. For the ACPI case, the _DSM helper is used to retrieve the QTG ID and returned. A devm_cxl_add_root() function is added for root port setup and registration of the cxl_root callback operation(s). Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/170319621294.2212653.1649682083061569256.stgit@djiang5-mobl3 Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dave Jiang
Dan Williams
parent
80aa780dda
commit
790815902e
@ -6,6 +6,7 @@
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/node.h>
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#include <asm/div64.h>
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#include "cxlpci.h"
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#include "cxl.h"
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@ -17,6 +18,10 @@ struct cxl_cxims_data {
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u64 xormaps[] __counted_by(nr_maps);
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};
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static const guid_t acpi_cxl_qtg_id_guid =
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GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
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0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
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/*
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* Find a targets entry (n) in the host bridge interleave list.
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* CXL Specification 3.0 Table 9-22
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@ -194,6 +199,125 @@ struct cxl_cfmws_context {
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int id;
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};
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/**
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* cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
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* @handle: ACPI handle
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* @coord: performance access coordinates
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* @entries: number of QTG IDs to return
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* @qos_class: int array provided by caller to return QTG IDs
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*
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* Return: number of QTG IDs returned, or -errno for errors
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*
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* Issue QTG _DSM with accompanied bandwidth and latency data in order to get
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* the QTG IDs that are suitable for the performance point in order of most
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* suitable to least suitable. Write back array of QTG IDs and return the
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* actual number of QTG IDs written back.
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*/
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static int
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cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
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int entries, int *qos_class)
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{
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union acpi_object *out_obj, *out_buf, *obj;
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union acpi_object in_array[4] = {
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[0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
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[1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
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[2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
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[3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
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};
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union acpi_object in_obj = {
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.package = {
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.type = ACPI_TYPE_PACKAGE,
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.count = 4,
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.elements = in_array,
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},
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};
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int count, pkg_entries, i;
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u16 max_qtg;
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int rc;
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if (!entries)
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return -EINVAL;
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out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
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if (!out_obj)
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return -ENXIO;
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if (out_obj->type != ACPI_TYPE_PACKAGE) {
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rc = -ENXIO;
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goto out;
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}
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/* Check Max QTG ID */
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obj = &out_obj->package.elements[0];
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if (obj->type != ACPI_TYPE_INTEGER) {
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rc = -ENXIO;
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goto out;
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}
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max_qtg = obj->integer.value;
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/* It's legal to have 0 QTG entries */
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pkg_entries = out_obj->package.count;
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if (pkg_entries <= 1) {
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rc = 0;
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goto out;
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}
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/* Retrieve QTG IDs package */
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obj = &out_obj->package.elements[1];
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if (obj->type != ACPI_TYPE_PACKAGE) {
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rc = -ENXIO;
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goto out;
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}
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pkg_entries = obj->package.count;
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count = min(entries, pkg_entries);
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for (i = 0; i < count; i++) {
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u16 qtg_id;
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out_buf = &obj->package.elements[i];
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if (out_buf->type != ACPI_TYPE_INTEGER) {
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rc = -ENXIO;
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goto out;
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}
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qtg_id = out_buf->integer.value;
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if (qtg_id > max_qtg)
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pr_warn("QTG ID %u greater than MAX %u\n",
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qtg_id, max_qtg);
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qos_class[i] = qtg_id;
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}
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rc = count;
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out:
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ACPI_FREE(out_obj);
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return rc;
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}
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static int cxl_acpi_qos_class(struct cxl_port *root_port,
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struct access_coordinate *coord, int entries,
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int *qos_class)
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{
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acpi_handle handle;
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struct device *dev;
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dev = root_port->uport_dev;
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if (!dev_is_platform(dev))
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return -ENODEV;
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handle = ACPI_HANDLE(dev);
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if (!handle)
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return -ENODEV;
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return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
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}
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static const struct cxl_root_ops acpi_root_ops = {
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.qos_class = cxl_acpi_qos_class,
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};
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static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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@ -656,6 +780,7 @@ static int cxl_acpi_probe(struct platform_device *pdev)
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{
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int rc;
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struct resource *cxl_res;
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struct cxl_root *cxl_root;
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struct cxl_port *root_port;
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struct device *host = &pdev->dev;
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struct acpi_device *adev = ACPI_COMPANION(host);
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@ -675,9 +800,10 @@ static int cxl_acpi_probe(struct platform_device *pdev)
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cxl_res->end = -1;
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cxl_res->flags = IORESOURCE_MEM;
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root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
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if (IS_ERR(root_port))
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return PTR_ERR(root_port);
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cxl_root = devm_cxl_add_root(host, &acpi_root_ops);
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if (IS_ERR(cxl_root))
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return PTR_ERR(cxl_root);
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root_port = &cxl_root->port;
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
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add_host_bridge_dport);
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@ -541,7 +541,10 @@ static void cxl_port_release(struct device *dev)
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xa_destroy(&port->dports);
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xa_destroy(&port->regions);
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ida_free(&cxl_port_ida, port->id);
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kfree(port);
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if (is_cxl_root(port))
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kfree(to_cxl_root(port));
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else
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kfree(port);
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}
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static ssize_t decoders_committed_show(struct device *dev,
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@ -669,17 +672,31 @@ static struct lock_class_key cxl_port_key;
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static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
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struct cxl_dport *parent_dport)
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{
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struct cxl_port *port;
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struct cxl_root *cxl_root __free(kfree) = NULL;
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struct cxl_port *port, *_port __free(kfree) = NULL;
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struct device *dev;
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int rc;
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port = kzalloc(sizeof(*port), GFP_KERNEL);
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if (!port)
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return ERR_PTR(-ENOMEM);
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/* No parent_dport, root cxl_port */
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if (!parent_dport) {
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cxl_root = kzalloc(sizeof(*cxl_root), GFP_KERNEL);
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if (!cxl_root)
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return ERR_PTR(-ENOMEM);
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} else {
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_port = kzalloc(sizeof(*port), GFP_KERNEL);
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if (!_port)
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return ERR_PTR(-ENOMEM);
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}
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rc = ida_alloc(&cxl_port_ida, GFP_KERNEL);
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if (rc < 0)
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goto err;
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return ERR_PTR(rc);
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if (cxl_root)
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port = &no_free_ptr(cxl_root)->port;
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else
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port = no_free_ptr(_port);
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port->id = rc;
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port->uport_dev = uport_dev;
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@ -731,10 +748,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
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dev->type = &cxl_port_type;
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return port;
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err:
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kfree(port);
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return ERR_PTR(rc);
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}
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static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
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@ -884,6 +897,22 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops)
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{
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struct cxl_root *cxl_root;
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struct cxl_port *port;
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port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
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if (IS_ERR(port))
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return (struct cxl_root *)port;
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cxl_root = to_cxl_root(port);
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cxl_root->ops = ops;
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return cxl_root;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, CXL);
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struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port)
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{
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/* There is no pci_bus associated with a CXL platform-root port */
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@ -615,6 +615,29 @@ struct cxl_port {
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bool cdat_available;
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};
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struct cxl_root_ops {
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int (*qos_class)(struct cxl_port *root_port,
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struct access_coordinate *coord, int entries,
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int *qos_class);
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};
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/**
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* struct cxl_root - logical collection of root cxl_port items
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*
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* @port: cxl_port member
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* @ops: cxl root operations
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*/
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struct cxl_root {
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struct cxl_port port;
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const struct cxl_root_ops *ops;
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};
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static inline struct cxl_root *
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to_cxl_root(const struct cxl_port *port)
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{
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return container_of(port, struct cxl_root, port);
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}
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static inline struct cxl_dport *
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cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
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{
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@ -703,6 +726,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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struct device *uport_dev,
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resource_size_t component_reg_phys,
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struct cxl_dport *parent_dport);
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops);
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struct cxl_port *find_cxl_root(struct cxl_port *port);
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int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
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void cxl_bus_rescan(void);
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