Cpufreq/arm updates for 5.20-rc1

- Fix return error code in mtk_cpu_dvfs_info_init (Yang Yingliang).
 
 - Minor cleanups and support for new boards for Qcom cpufreq drivers
   (Bryan O'Donoghue, Konrad Dybcio, Pierre Gondois, and Yicong Yang).
 
 - Fix sparse warnings for Tegra driver (Viresh Kumar).
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Merge tag 'cpufreq-arm-updates-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm

Pull cpufreq/ARM updates for 5.20-rc1 from Viresh Kumar:

"- Fix return error code in mtk_cpu_dvfs_info_init (Yang Yingliang).

 - Minor cleanups and support for new boards for Qcom cpufreq drivers
   (Bryan O'Donoghue, Konrad Dybcio, Pierre Gondois, and Yicong Yang).

 - Fix sparse warnings for Tegra driver (Viresh Kumar)."

* tag 'cpufreq-arm-updates-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm:
  cpufreq: tegra194: Staticize struct tegra_cpufreq_soc instances
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6375 compatible
  dt-bindings: opp: Add msm8939 to the compatible list
  dt-bindings: opp: Add missing compat devices
  dt-bindings: opp: opp-v2-kryo-cpu: Fix example binding checks
  cpufreq: Change order of online() CB and policy->cpus modification
  cpufreq: qcom-hw: Remove deprecated irq_set_affinity_hint() call
  cpufreq: qcom-hw: Disable LMH irq when disabling policy
  cpufreq: qcom-hw: Reset cancel_throttle when policy is re-enabled
  cpufreq: qcom-cpufreq-hw: use HZ_PER_KHZ macro in units.h
  cpufreq: mediatek: fix error return code in mtk_cpu_dvfs_info_init()
This commit is contained in:
Rafael J. Wysocki 2022-08-03 17:47:45 +02:00
commit 7912c9c6a6
7 changed files with 38 additions and 10 deletions

View File

@ -25,6 +25,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS) - description: v2 of CPUFREQ HW (EPSS)
items: items:
- enum: - enum:
- qcom,sm6375-cpufreq-epss
- qcom,sm8250-cpufreq-epss - qcom,sm8250-cpufreq-epss
- const: qcom,cpufreq-epss - const: qcom,cpufreq-epss

View File

@ -22,6 +22,13 @@ select:
compatible: compatible:
contains: contains:
enum: enum:
- qcom,apq8064
- qcom,apq8096
- qcom,ipq8064
- qcom,msm8939
- qcom,msm8960
- qcom,msm8974
- qcom,msm8996
- qcom,qcs404 - qcom,qcs404
required: required:
- compatible - compatible

View File

@ -98,6 +98,8 @@ examples:
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>; clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>; #cooling-cells = <2>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
L2_0: l2-cache { L2_0: l2-cache {
@ -115,6 +117,8 @@ examples:
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>; clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>; #cooling-cells = <2>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
}; };
@ -128,6 +132,8 @@ examples:
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>; clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>; #cooling-cells = <2>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
L2_1: l2-cache { L2_1: l2-cache {
@ -145,6 +151,8 @@ examples:
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>; clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
power-domains = <&cpr>;
power-domain-names = "cpr";
#cooling-cells = <2>; #cooling-cells = <2>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
}; };
@ -182,18 +190,21 @@ examples:
opp-microvolt = <905000 905000 1140000>; opp-microvolt = <905000 905000 1140000>;
opp-supported-hw = <0x7>; opp-supported-hw = <0x7>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp1>;
}; };
opp-1401600000 { opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>; opp-hz = /bits/ 64 <1401600000>;
opp-microvolt = <1140000 905000 1140000>; opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x5>; opp-supported-hw = <0x5>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp2>;
}; };
opp-1593600000 { opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>; opp-hz = /bits/ 64 <1593600000>;
opp-microvolt = <1140000 905000 1140000>; opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x1>; opp-supported-hw = <0x1>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp3>;
}; };
}; };
@ -207,24 +218,28 @@ examples:
opp-microvolt = <905000 905000 1140000>; opp-microvolt = <905000 905000 1140000>;
opp-supported-hw = <0x7>; opp-supported-hw = <0x7>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp1>;
}; };
opp-1804800000 { opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>; opp-hz = /bits/ 64 <1804800000>;
opp-microvolt = <1140000 905000 1140000>; opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x6>; opp-supported-hw = <0x6>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp4>;
}; };
opp-1900800000 { opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>; opp-hz = /bits/ 64 <1900800000>;
opp-microvolt = <1140000 905000 1140000>; opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x4>; opp-supported-hw = <0x4>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp5>;
}; };
opp-2150400000 { opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>; opp-hz = /bits/ 64 <2150400000>;
opp-microvolt = <1140000 905000 1140000>; opp-microvolt = <1140000 905000 1140000>;
opp-supported-hw = <0x1>; opp-supported-hw = <0x1>;
clock-latency-ns = <200000>; clock-latency-ns = <200000>;
required-opps = <&cpr_opp6>;
}; };
}; };

View File

@ -1348,15 +1348,15 @@ static int cpufreq_online(unsigned int cpu)
} }
if (!new_policy && cpufreq_driver->online) { if (!new_policy && cpufreq_driver->online) {
/* Recover policy->cpus using related_cpus */
cpumask_copy(policy->cpus, policy->related_cpus);
ret = cpufreq_driver->online(policy); ret = cpufreq_driver->online(policy);
if (ret) { if (ret) {
pr_debug("%s: %d: initialization failed\n", __func__, pr_debug("%s: %d: initialization failed\n", __func__,
__LINE__); __LINE__);
goto out_exit_policy; goto out_exit_policy;
} }
/* Recover policy->cpus using related_cpus */
cpumask_copy(policy->cpus, policy->related_cpus);
} else { } else {
cpumask_copy(policy->cpus, cpumask_of(cpu)); cpumask_copy(policy->cpus, cpumask_of(cpu));

View File

@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
if (info->soc_data->ccifreq_supported) { if (info->soc_data->ccifreq_supported) {
info->vproc_on_boot = regulator_get_voltage(info->proc_reg); info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
if (info->vproc_on_boot < 0) { if (info->vproc_on_boot < 0) {
ret = info->vproc_on_boot;
dev_err(info->cpu_dev, dev_err(info->cpu_dev,
"invalid Vproc value: %d\n", info->vproc_on_boot); "invalid Vproc value: %d\n", info->vproc_on_boot);
goto out_disable_inter_clock; goto out_disable_inter_clock;

View File

@ -15,6 +15,7 @@
#include <linux/pm_opp.h> #include <linux/pm_opp.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/units.h>
#define LUT_MAX_ENTRIES 40U #define LUT_MAX_ENTRIES 40U
#define LUT_SRC GENMASK(31, 30) #define LUT_SRC GENMASK(31, 30)
@ -26,8 +27,6 @@
#define GT_IRQ_STATUS BIT(2) #define GT_IRQ_STATUS BIT(2)
#define HZ_PER_KHZ 1000
struct qcom_cpufreq_soc_data { struct qcom_cpufreq_soc_data {
u32 reg_enable; u32 reg_enable;
u32 reg_domain_state; u32 reg_domain_state;
@ -428,7 +427,7 @@ static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
return 0; return 0;
} }
ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus); ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
if (ret) if (ret)
dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
data->irq_name, data->throttle_irq); data->irq_name, data->throttle_irq);
@ -445,7 +444,11 @@ static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
if (data->throttle_irq <= 0) if (data->throttle_irq <= 0)
return 0; return 0;
ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus); mutex_lock(&data->throttle_lock);
data->cancel_throttle = false;
mutex_unlock(&data->throttle_lock);
ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
if (ret) if (ret)
dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
data->irq_name, data->throttle_irq); data->irq_name, data->throttle_irq);
@ -465,7 +468,8 @@ static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
mutex_unlock(&data->throttle_lock); mutex_unlock(&data->throttle_lock);
cancel_delayed_work_sync(&data->throttle_work); cancel_delayed_work_sync(&data->throttle_work);
irq_set_affinity_hint(data->throttle_irq, NULL); irq_set_affinity_and_hint(data->throttle_irq, NULL);
disable_irq_nosync(data->throttle_irq);
return 0; return 0;
} }

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@ -162,7 +162,7 @@ static struct tegra_cpufreq_ops tegra234_cpufreq_ops = {
.set_cpu_ndiv = tegra234_set_cpu_ndiv, .set_cpu_ndiv = tegra234_set_cpu_ndiv,
}; };
const struct tegra_cpufreq_soc tegra234_cpufreq_soc = { static const struct tegra_cpufreq_soc tegra234_cpufreq_soc = {
.ops = &tegra234_cpufreq_ops, .ops = &tegra234_cpufreq_ops,
.actmon_cntr_base = 0x9000, .actmon_cntr_base = 0x9000,
.maxcpus_per_cluster = 4, .maxcpus_per_cluster = 4,
@ -430,7 +430,7 @@ static struct tegra_cpufreq_ops tegra194_cpufreq_ops = {
.set_cpu_ndiv = tegra194_set_cpu_ndiv, .set_cpu_ndiv = tegra194_set_cpu_ndiv,
}; };
const struct tegra_cpufreq_soc tegra194_cpufreq_soc = { static const struct tegra_cpufreq_soc tegra194_cpufreq_soc = {
.ops = &tegra194_cpufreq_ops, .ops = &tegra194_cpufreq_ops,
.maxcpus_per_cluster = 2, .maxcpus_per_cluster = 2,
}; };