Cpufreq/arm updates for 5.20-rc1
- Fix return error code in mtk_cpu_dvfs_info_init (Yang Yingliang). - Minor cleanups and support for new boards for Qcom cpufreq drivers (Bryan O'Donoghue, Konrad Dybcio, Pierre Gondois, and Yicong Yang). - Fix sparse warnings for Tegra driver (Viresh Kumar). -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEx73Crsp7f6M6scA70rkcPK6BEhwFAmLoqRYACgkQ0rkcPK6B EhzcNA/6A52UpkbXwfd63B+hCeLPTjjvnn+Z1FeRUG+ymbEDcMYQ7Z+ae3clKQ86 MmkK9UkYae50riCz9lv10UihI5JtxVkyCiCvgASxmRAvKrbODqSOu0UmMKR+CwJ/ GryoB8xCL/aAencyb3qin4fZHlwdjqBP7mgRQtoRbxjT0liFonauoG84DPhWhgMi i22V83j4pZpDIPyfNN9AvBOiaGXx3n3zG0ODx1E7Y7P9Eg/3n1AdRPST3C4Y4y3X 79WbwBur13NKi9Ww5jw5guRKehNC8l79Ly80UQ4pRg2y4RtmyABX9qteOfvbj9Ix JFWV+EdDLhU+mk1hHMx3GzFDWsaUYS+ZrS9oDREZ06LkN1ZDf5OFOP8nxr7SRvSD 3ZYlVA2IClt1Q//GsRiGy7kJK1qFtWVVWEE/NHS27W6VorugoHiyfNx8jYYBaOez bNyrKklYlIFsgkRoVG0e2/2ZrzCeTVZLjsFl9992pnoDG8Fv9fBUpsHQajLkolJ4 KSZ35sxSvMzREKtuy4g8XeV2l9cES5FZ6B2iGqVo2BuoJdyqMfcQqtOyVbXAlkOz pXSPxVuNr5w9uVQhuE0cSAiqe6joMgE5jT+5A2dIThC34nRzDLTrmQohR31nDZRj nCsb3Pkee6j8DVwGVSNFuVJ0xvOnw1Sk8RCidiKZ9+Otu/blqaM= =fX64 -----END PGP SIGNATURE----- Merge tag 'cpufreq-arm-updates-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Pull cpufreq/ARM updates for 5.20-rc1 from Viresh Kumar: "- Fix return error code in mtk_cpu_dvfs_info_init (Yang Yingliang). - Minor cleanups and support for new boards for Qcom cpufreq drivers (Bryan O'Donoghue, Konrad Dybcio, Pierre Gondois, and Yicong Yang). - Fix sparse warnings for Tegra driver (Viresh Kumar)." * tag 'cpufreq-arm-updates-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: tegra194: Staticize struct tegra_cpufreq_soc instances dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6375 compatible dt-bindings: opp: Add msm8939 to the compatible list dt-bindings: opp: Add missing compat devices dt-bindings: opp: opp-v2-kryo-cpu: Fix example binding checks cpufreq: Change order of online() CB and policy->cpus modification cpufreq: qcom-hw: Remove deprecated irq_set_affinity_hint() call cpufreq: qcom-hw: Disable LMH irq when disabling policy cpufreq: qcom-hw: Reset cancel_throttle when policy is re-enabled cpufreq: qcom-cpufreq-hw: use HZ_PER_KHZ macro in units.h cpufreq: mediatek: fix error return code in mtk_cpu_dvfs_info_init()
This commit is contained in:
commit
7912c9c6a6
@ -25,6 +25,7 @@ properties:
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- description: v2 of CPUFREQ HW (EPSS)
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- description: v2 of CPUFREQ HW (EPSS)
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items:
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items:
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- enum:
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- enum:
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- qcom,sm6375-cpufreq-epss
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- qcom,sm8250-cpufreq-epss
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- qcom,sm8250-cpufreq-epss
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- const: qcom,cpufreq-epss
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- const: qcom,cpufreq-epss
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@ -22,6 +22,13 @@ select:
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compatible:
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compatible:
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contains:
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contains:
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enum:
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enum:
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- qcom,apq8064
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- qcom,apq8096
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- qcom,ipq8064
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- qcom,msm8939
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- qcom,msm8960
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- qcom,msm8974
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- qcom,msm8996
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- qcom,qcs404
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- qcom,qcs404
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required:
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required:
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- compatible
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- compatible
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@ -98,6 +98,8 @@ examples:
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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operating-points-v2 = <&cluster0_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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L2_0: l2-cache {
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@ -115,6 +117,8 @@ examples:
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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operating-points-v2 = <&cluster0_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&L2_0>;
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};
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};
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@ -128,6 +132,8 @@ examples:
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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operating-points-v2 = <&cluster1_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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L2_1: l2-cache {
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@ -145,6 +151,8 @@ examples:
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capacity-dmips-mhz = <1024>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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operating-points-v2 = <&cluster1_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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};
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};
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@ -182,18 +190,21 @@ examples:
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opp-microvolt = <905000 905000 1140000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp1>;
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};
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};
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opp-1401600000 {
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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opp-hz = /bits/ 64 <1401600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x5>;
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opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp2>;
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};
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};
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opp-1593600000 {
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opp-1593600000 {
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opp-hz = /bits/ 64 <1593600000>;
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opp-hz = /bits/ 64 <1593600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x1>;
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opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp3>;
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};
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};
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};
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};
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@ -207,24 +218,28 @@ examples:
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opp-microvolt = <905000 905000 1140000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp1>;
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};
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};
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opp-1804800000 {
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opp-1804800000 {
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opp-hz = /bits/ 64 <1804800000>;
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opp-hz = /bits/ 64 <1804800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x6>;
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opp-supported-hw = <0x6>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp4>;
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};
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};
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opp-1900800000 {
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opp-1900800000 {
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opp-hz = /bits/ 64 <1900800000>;
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opp-hz = /bits/ 64 <1900800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x4>;
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opp-supported-hw = <0x4>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp5>;
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};
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};
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opp-2150400000 {
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opp-2150400000 {
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opp-hz = /bits/ 64 <2150400000>;
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opp-hz = /bits/ 64 <2150400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x1>;
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opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp6>;
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};
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};
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};
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};
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@ -1348,15 +1348,15 @@ static int cpufreq_online(unsigned int cpu)
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}
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}
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if (!new_policy && cpufreq_driver->online) {
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if (!new_policy && cpufreq_driver->online) {
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/* Recover policy->cpus using related_cpus */
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cpumask_copy(policy->cpus, policy->related_cpus);
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ret = cpufreq_driver->online(policy);
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ret = cpufreq_driver->online(policy);
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if (ret) {
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if (ret) {
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pr_debug("%s: %d: initialization failed\n", __func__,
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pr_debug("%s: %d: initialization failed\n", __func__,
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__LINE__);
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__LINE__);
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goto out_exit_policy;
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goto out_exit_policy;
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}
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}
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/* Recover policy->cpus using related_cpus */
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cpumask_copy(policy->cpus, policy->related_cpus);
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} else {
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} else {
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cpumask_copy(policy->cpus, cpumask_of(cpu));
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cpumask_copy(policy->cpus, cpumask_of(cpu));
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@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
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if (info->soc_data->ccifreq_supported) {
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if (info->soc_data->ccifreq_supported) {
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info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
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info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
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if (info->vproc_on_boot < 0) {
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if (info->vproc_on_boot < 0) {
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ret = info->vproc_on_boot;
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dev_err(info->cpu_dev,
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dev_err(info->cpu_dev,
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"invalid Vproc value: %d\n", info->vproc_on_boot);
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"invalid Vproc value: %d\n", info->vproc_on_boot);
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goto out_disable_inter_clock;
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goto out_disable_inter_clock;
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@ -15,6 +15,7 @@
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#include <linux/pm_opp.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/spinlock.h>
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#include <linux/units.h>
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#define LUT_MAX_ENTRIES 40U
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_SRC GENMASK(31, 30)
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@ -26,8 +27,6 @@
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#define GT_IRQ_STATUS BIT(2)
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#define GT_IRQ_STATUS BIT(2)
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#define HZ_PER_KHZ 1000
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struct qcom_cpufreq_soc_data {
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struct qcom_cpufreq_soc_data {
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u32 reg_enable;
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u32 reg_enable;
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u32 reg_domain_state;
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u32 reg_domain_state;
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@ -428,7 +427,7 @@ static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
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return 0;
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return 0;
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}
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}
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ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
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ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
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if (ret)
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if (ret)
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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data->irq_name, data->throttle_irq);
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data->irq_name, data->throttle_irq);
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@ -445,7 +444,11 @@ static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
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if (data->throttle_irq <= 0)
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if (data->throttle_irq <= 0)
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return 0;
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return 0;
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ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
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mutex_lock(&data->throttle_lock);
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data->cancel_throttle = false;
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mutex_unlock(&data->throttle_lock);
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ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
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if (ret)
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if (ret)
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
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data->irq_name, data->throttle_irq);
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data->irq_name, data->throttle_irq);
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@ -465,7 +468,8 @@ static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
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mutex_unlock(&data->throttle_lock);
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mutex_unlock(&data->throttle_lock);
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cancel_delayed_work_sync(&data->throttle_work);
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cancel_delayed_work_sync(&data->throttle_work);
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irq_set_affinity_hint(data->throttle_irq, NULL);
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irq_set_affinity_and_hint(data->throttle_irq, NULL);
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disable_irq_nosync(data->throttle_irq);
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return 0;
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return 0;
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}
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}
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@ -162,7 +162,7 @@ static struct tegra_cpufreq_ops tegra234_cpufreq_ops = {
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.set_cpu_ndiv = tegra234_set_cpu_ndiv,
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.set_cpu_ndiv = tegra234_set_cpu_ndiv,
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};
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};
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const struct tegra_cpufreq_soc tegra234_cpufreq_soc = {
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static const struct tegra_cpufreq_soc tegra234_cpufreq_soc = {
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.ops = &tegra234_cpufreq_ops,
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.ops = &tegra234_cpufreq_ops,
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.actmon_cntr_base = 0x9000,
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.actmon_cntr_base = 0x9000,
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.maxcpus_per_cluster = 4,
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.maxcpus_per_cluster = 4,
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@ -430,7 +430,7 @@ static struct tegra_cpufreq_ops tegra194_cpufreq_ops = {
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.set_cpu_ndiv = tegra194_set_cpu_ndiv,
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.set_cpu_ndiv = tegra194_set_cpu_ndiv,
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};
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};
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const struct tegra_cpufreq_soc tegra194_cpufreq_soc = {
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static const struct tegra_cpufreq_soc tegra194_cpufreq_soc = {
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.ops = &tegra194_cpufreq_ops,
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.ops = &tegra194_cpufreq_ops,
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.maxcpus_per_cluster = 2,
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.maxcpus_per_cluster = 2,
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};
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};
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