Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: smp_on_up: allow non-ARM SMP processors ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+ ARM: initrd: disable initrd if passed address overlaps reserved region ARM: footbridge: fix debug macros ARM: mmci: round down the bytes transferred on error ARM: mmci: complete the transaction on error ARM: 6642/1: mmci: calculate remaining bytes at error correctly
This commit is contained in:
Linus Torvalds
commit
7921127e29
@ -95,6 +95,15 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
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return (void __iomem *)addr;
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}
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/* IO barriers */
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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@ -125,17 +134,17 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#ifdef __io
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#define outb(v,p) __raw_writeb(v,__io(p))
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#define outw(v,p) __raw_writew((__force __u16) \
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cpu_to_le16(v),__io(p))
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#define outl(v,p) __raw_writel((__force __u32) \
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cpu_to_le32(v),__io(p))
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#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
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#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
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cpu_to_le16(v),__io(p)); })
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#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
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cpu_to_le32(v),__io(p)); })
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#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; })
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#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
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#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
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__raw_readw(__io(p))); __v; })
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__raw_readw(__io(p))); __iormb(); __v; })
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#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
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__raw_readl(__io(p))); __v; })
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__raw_readl(__io(p))); __iormb(); __v; })
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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@ -192,14 +201,6 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v),__mem_pci(c)))
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on)
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#ifdef CONFIG_SMP_ON_UP
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__fixup_smp:
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mov r4, #0x00070000
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orr r3, r4, #0xff000000 @ mask 0xff070000
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orr r4, r4, #0x41000000 @ val 0x41070000
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and r0, r9, r3
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teq r0, r4 @ ARM CPU and ARMv6/v7?
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and r3, r9, #0x000f0000 @ architecture version
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teq r3, #0x000f0000 @ CPU ID supported?
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bne __fixup_smp_on_up @ no, assume UP
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orr r3, r3, #0x0000ff00
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orr r3, r3, #0x000000f0 @ mask 0xff07fff0
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bic r3, r9, #0x00ff0000
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bic r3, r3, #0x0000000f @ mask 0xff00fff0
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mov r4, #0x41000000
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orr r4, r4, #0x0000b000
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orr r4, r4, #0x00000020 @ val 0x4107b020
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and r0, r9, r3
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teq r0, r4 @ ARM 11MPCore?
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orr r4, r4, #0x00000020 @ val 0x4100b020
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teq r3, r4 @ ARM 11MPCore?
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moveq pc, lr @ yes, assume SMP
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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tst r0, #1 << 31
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movne pc, lr @ bit 31 => SMP
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and r0, r0, #0xc0000000 @ multiprocessing extensions and
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teq r0, #0x80000000 @ not part of a uniprocessor system?
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moveq pc, lr @ yes, assume SMP
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__fixup_smp_on_up:
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adr r0, 1f
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@ -17,8 +17,8 @@
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/* For NetWinder debugging */
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.macro addruart, rp, rv
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mov \rp, #0x000003f8
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orr \rv, \rp, #0x7c000000 @ physical
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orr \rp, \rp, #0xff000000 @ virtual
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orr \rv, \rp, #0xff000000 @ virtual
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orr \rp, \rp, #0x7c000000 @ physical
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.endm
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#define UART_SHIFT 0
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@ -297,6 +297,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
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memblock_reserve(__pa(_stext), _end - _stext);
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#endif
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#ifdef CONFIG_BLK_DEV_INITRD
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if (phys_initrd_size &&
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memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
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pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
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phys_initrd_start, phys_initrd_size);
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phys_initrd_start = phys_initrd_size = 0;
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}
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if (phys_initrd_size) {
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memblock_reserve(phys_initrd_start, phys_initrd_size);
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@ -14,6 +14,7 @@
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/highmem.h>
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@ -283,19 +284,19 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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u32 remain, success;
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/* Calculate how far we are into the transfer */
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remain = readl(host->base + MMCIDATACNT) << 2;
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remain = readl(host->base + MMCIDATACNT);
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success = data->blksz * data->blocks - remain;
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dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
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if (status & MCI_DATACRCFAIL) {
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/* Last block was not successful */
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host->data_xfered = ((success / data->blksz) - 1 * data->blksz);
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host->data_xfered = round_down(success - 1, data->blksz);
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data->error = -EILSEQ;
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} else if (status & MCI_DATATIMEOUT) {
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host->data_xfered = success;
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host->data_xfered = round_down(success, data->blksz);
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data->error = -ETIMEDOUT;
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} else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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host->data_xfered = success;
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host->data_xfered = round_down(success, data->blksz);
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data->error = -EIO;
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}
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@ -319,7 +320,7 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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if (status & MCI_DATABLOCKEND)
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dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
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if (status & MCI_DATAEND) {
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if (status & MCI_DATAEND || data->error) {
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mmci_stop_data(host);
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if (!data->error)
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