clk: samsung: exynos7: Add required clock tree for UFS
Adding required mux/div/gate clocks for UFS controller present on Exynos7. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Alim Akhtar
Sylwester Nawrocki
parent
ad108e10ae
commit
7993b3ebec
@ -477,12 +477,21 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
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MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
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MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
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MUX_SEL_TOP1_FSYS0, 0, 2),
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MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
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MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
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MUX_SEL_TOP1_FSYS0, 28, 2),
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MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
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MUX_SEL_TOP1_FSYS1, 0, 2),
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MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
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MUX_SEL_TOP1_FSYS1, 16, 2),
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MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
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MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
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MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
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MUX_SEL_TOP1_FSYS11, 24, 2),
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};
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static struct samsung_div_clock top1_div_clks[] __initdata = {
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@ -491,6 +500,13 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
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DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
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DIV_TOP13, 28, 4),
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DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
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"mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
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DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
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"mout_sclk_ufsunipro20",
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DIV_TOP1_FSYS1, 16, 6),
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DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
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DIV_TOP1_FSYS0, 16, 10),
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DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
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@ -500,6 +516,9 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
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DIV_TOP1_FSYS11, 0, 10),
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DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
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DIV_TOP1_FSYS11, 12, 10),
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DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
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"mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
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};
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static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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@ -508,6 +527,12 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
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ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
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GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
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ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
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ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
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ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
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@ -517,6 +542,10 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
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ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
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"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
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24, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
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@ -956,22 +985,54 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
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/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
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#define MUX_SEL_FSYS10 0x0200
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#define MUX_SEL_FSYS11 0x0204
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#define MUX_SEL_FSYS12 0x0208
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#define DIV_FSYS1 0x0600
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#define ENABLE_ACLK_FSYS1 0x0800
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#define ENABLE_PCLK_FSYS1 0x0900
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#define ENABLE_SCLK_FSYS11 0x0A04
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#define ENABLE_SCLK_FSYS12 0x0A08
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#define ENABLE_SCLK_FSYS13 0x0A0C
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/*
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* List of parent clocks for Muxes in CMU_FSYS1
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*/
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PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
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PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
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"sclk_phy_fsys1_26m" };
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PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
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PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
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PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
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PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
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PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
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PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
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/* fixed rate clocks used in the FSYS1 block */
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struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
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FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
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CLK_IS_ROOT, 300000000),
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FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
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CLK_IS_ROOT, 300000000),
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FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
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CLK_IS_ROOT, 300000000),
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};
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static unsigned long fsys1_clk_regs[] __initdata = {
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MUX_SEL_FSYS10,
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MUX_SEL_FSYS11,
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MUX_SEL_FSYS12,
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DIV_FSYS1,
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ENABLE_ACLK_FSYS1,
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ENABLE_PCLK_FSYS1,
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ENABLE_SCLK_FSYS11,
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ENABLE_SCLK_FSYS12,
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ENABLE_SCLK_FSYS13,
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};
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static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
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MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
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mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
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MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
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MUX_SEL_FSYS10, 20, 2),
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MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
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MUX_SEL_FSYS10, 28, 1),
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@ -979,18 +1040,64 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
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MUX_SEL_FSYS11, 24, 1),
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MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
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MUX_SEL_FSYS11, 28, 1),
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MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
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MUX_SEL_FSYS11, 20, 1),
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MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
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mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
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MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
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mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
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MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
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mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
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};
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static struct samsung_div_clock fsys1_div_clks[] __initdata = {
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DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
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DIV_FSYS1, 0, 2),
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};
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static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
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GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
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"mout_sclk_ufsunipro20_user",
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ENABLE_SCLK_FSYS11, 20, 0, 0),
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GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
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ENABLE_ACLK_FSYS1, 29, 0, 0),
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GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
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ENABLE_ACLK_FSYS1, 30, 0, 0),
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GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
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ENABLE_ACLK_FSYS1, 31, 0, 0),
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GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
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ENABLE_PCLK_FSYS1, 30, 0, 0),
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GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
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"mout_phyclk_ufs20_rx1_symbol_user",
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ENABLE_SCLK_FSYS12, 16, 0, 0),
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GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
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"mout_phyclk_ufs20_rx0_symbol_user",
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ENABLE_SCLK_FSYS12, 24, 0, 0),
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GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
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"mout_phyclk_ufs20_tx0_symbol_user",
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ENABLE_SCLK_FSYS12, 28, 0, 0),
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GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
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"oscclk_phy_clkout_embedded_combo_phy",
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"fin_pll",
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ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
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GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
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"mout_fsys1_phyclk_sel1",
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ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info fsys1_cmu_info __initdata = {
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.fixed_clks = fixed_rate_clks_fsys1,
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.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
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.mux_clks = fsys1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
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.div_clks = fsys1_div_clks,
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.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
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.gate_clks = fsys1_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
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.nr_clk_ids = FSYS1_NR_CLK,
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@ -64,7 +64,14 @@
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#define CLK_SCLK_MMC0 8
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#define CLK_ACLK_FSYS0_200 9
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#define CLK_ACLK_FSYS1_200 10
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#define TOP1_NR_CLK 11
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#define CLK_SCLK_PHY_FSYS1 11
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#define CLK_SCLK_PHY_FSYS1_26M 12
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#define MOUT_SCLK_UFSUNIPRO20 13
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#define DOUT_SCLK_UFSUNIPRO20 14
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#define CLK_SCLK_UFSUNIPRO20 15
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#define DOUT_SCLK_PHY_FSYS1 16
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#define DOUT_SCLK_PHY_FSYS1_26M 17
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#define TOP1_NR_CLK 18
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/* CCORE */
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#define PCLK_RTC 1
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@ -139,7 +146,20 @@
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/* FSYS1 */
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#define ACLK_MMC1 1
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#define ACLK_MMC0 2
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#define FSYS1_NR_CLK 3
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#define PHYCLK_UFS20_TX0_SYMBOL 3
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#define PHYCLK_UFS20_RX0_SYMBOL 4
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#define PHYCLK_UFS20_RX1_SYMBOL 5
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#define ACLK_UFS20_LINK 6
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#define SCLK_UFSUNIPRO20_USER 7
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#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
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#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
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#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
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#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
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#define SCLK_COMBO_PHY_EMBEDDED_26M 12
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#define DOUT_PCLK_FSYS1 13
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#define PCLK_GPIO_FSYS1 14
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#define MOUT_FSYS1_PHYCLK_SEL1 15
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#define FSYS1_NR_CLK 16
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/* MSCL */
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#define USERMUX_ACLK_MSCL_532 1
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